Conferences in DBLP
David R. Ditzel , Hubert R. McLellan Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero. [Citation Graph (0, 0)][DBLP ] Conf ] John A. DeRosa , Henry M. Levy An Evaluation of Branch Architectures [Citation Graph (0, 0)][DBLP ] Conf ] Wen-mei W. Hwu , Yale N. Patt Checkpoint Repair for Out-of-order Execution Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Gurindar S. Sohi , Sriram Vajapeyam Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Swensen , Yale N. Patt Fast Temporary Storage for Serial and Parallel Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth F. Wong , Mark A. Franklin Performance Analysis and Design of a Logic Simulation Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Kshitij Doshi , Peter J. Varman A Modular Systolic Architecture for Image Convolutions. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Fujita , Reiji Aibara , Masafumi Yamashita , Tadashi Ae A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bilha Mendelson , Gabriel M. Silberman Mapping Data Flow Programs on a VLSI Array of Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Dipak Ghosal , Laxmi N. Bhuyan Analytical Modeling and Architectural Modifications of a Dataflow Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Masaru Takesue A Unified Resource Management and Execution Control Mechanism for Data Flow Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeo Abe , Tadaaki Bandoh , S. Yamaguchi , Ken-ichi Kurosawa , Kaori Kiriyama High Performance Integrated Prolog Processor IPP. [Citation Graph (0, 0)][DBLP ] Conf ] Barry S. Fagin , Alvin M. Despain Performance Studies of a Parallel Prolog Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Pierluigi Civera , F. Maddaleno , Gianluca Piccinini , Maurizio Zamboni An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Ridoux Deterministic and Stochastic Modeling of Parallel Garbage Collection -- Towards Real-Time Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Chengzheng Sun , Tzu Yungui The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Aloke Guha , Raja Ramnarayan , Matthew Derstine Architectural Issues in Designing Symbolic Processors in Optics. [Citation Graph (0, 0)][DBLP ] Conf ] Anujan Varma , C. S. Raghavendra Rearrangeability of Multistage Shuffle/Exchange Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ramón Beivide , Enrique Herrada , José L. Balcázar , Jesús Labarta Optimized Mesh-Connected Networks for SIMD and MIMD Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] David T. Harper III , J. Robert Jump Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Umakishore Ramachandran , Marvin H. Solomon , Mary K. Vernon Hardware Support for Interprocess Communication. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Dally , Linda Chao , Andrew A. Chien , Soha Hassoun , Waldemar Horwat , Jon Kaplan , Paul Song , Brian Totty , D. Scott Wills Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] J. H. Chang , H. Chao , Kimming So Cache Design of a Sub-Micron CMOS System/370. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Freeman An Architectural Perspective on a Memory Access Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Kifung C. Cheung , Gurindar S. Sohi , Kewal K. Saluja , Dhiraj K. Pradhan Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scheurich , Michel Dubois Correct Memory Operation of Cache-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew W. Wilson Jr. Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Roland L. Lee , Pen-Chung Yew , Duncan H. Lawrie Multiprocessor Cache Design Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Eickemeyer , Janak H. Patel Performance Evaluation of Multiple Register Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Stanley , Robert G. Wedig A Performance Analysis of Automatically Managed Top of Stack Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Brian B. Moore , Andris Padegs , Ronald M. Smith , Werner Buchholz Concepts of the System/370 Vector Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew R. Pleszkun , James R. Goodman , Wei-Chung Hsu , R. T. Joersz , George E. Bier , Philip J. Woest , P. B. Schechter WISQ: A Restartable Architecture Using Queues. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Chow , Mark Horowitz Architectural Tradeoffs in the Design of MIPS-X. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Ditzel , Hubert R. McLellan , Alan D. Berenbaum The Hardware Architecture of the CRISP Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] 