The SCEAS System
Navigation Menu

Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2001 (conf/isca/2001)

  1. Craig B. Zilles, Gurindar S. Sohi
    Execution-based prediction using speculative slices. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:2-13 [Conf]
  2. Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
    Speculative precomputation: long-range prefetching of delinquent loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:14-25 [Conf]
  3. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically allocating processor resources between nearby and distant ILP. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:26-37 [Conf]
  4. Chi-Keung Luk
    Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:40-51 [Conf]
  5. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
    Data prefetching by dependence graph precomputation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:52-61 [Conf]
  6. Vinodh Cuppu, Bruce L. Jacob
    Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:62-71 [Conf]
  7. Brian A. Fields, Shai Rubin, Rastislav Bodík
    Focusing processor policies via critical-path prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:74-85 [Conf]
  8. Timothy Sherwood, Brad Calder
    Automated design of finite state machine predictors for customized processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:86-97 [Conf]
  9. Youfeng Wu, Dong-yuan Chen, Jesse Fang
    Better exploration of region-level value locality with integrated computation reuse and value prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:98-108 [Conf]
  10. Lisa Wu, Chris Weaver, Todd M. Austin
    CryptoManiac: a fast flexible architecture for secure communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:110-119 [Conf]
  11. Ki Hwan Yum, Eun Jung Kim, Chita R. Das
    QoS provisioning in clusters: an investigation of Router and NIC design. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:120-129 [Conf]
  12. Srikanth T. Srinivasan, Roy Dz-Ching Ju, Alvin R. Lebeck, Chris Wilkerson
    Locality vs. criticality. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:132-143 [Conf]
  13. An-Chow Lai, Cem Fide, Babak Falsafi
    Dead-block prediction & dead-block correlating prefetchers. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:144-154 [Conf]
  14. Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
    Code layout optimizations for transaction processing workloads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:155-164 [Conf]
  15. Michael T. Niemier, Peter M. Kogge
    Exploring and exploiting wire-level pipelining in emerging technologies. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:166-177 [Conf]
  16. Seth Copen Goldstein, Mihai Budiu
    NanoFabrics: spatial computing using molecular electronics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:178-191 [Conf]
  17. David Lie, Andy Chou, Dawson R. Engler, David L. Dill
    A simple method for extracting models for protocol code. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:192-203 [Conf]
  18. Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas
    Removing architectural bottlenecks to the scalability of speculative parallelization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:204-215 [Conf]
  19. R. Iris Bahar, Srilatha Manne
    Power and energy reduction via pipeline balancing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:218-229 [Conf]
  20. Daniele Folegnani, Antonio González
    Energy-effective issue logic. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:230-239 [Conf]
  21. Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
    Cache decay: exploiting generational behavior to reduce cache leakage power. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:240-251 [Conf]
  22. Christopher J. Hughes, Praful Kaul, Sarita V. Adve, Rohit Jain, Chanik Park, Jayanth Srinivasan
    Variability in the execution of multimedia applications and implications for architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:254-265 [Conf]
  23. S. Subramanya Sastry, Rastislav Bodík, James E. Smith
    Rapid profiling via stratified sampling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:278-289 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002