Conferences in DBLP
Ronald F. DeMara , Dan I. Moldovan The SNAP-1 Parallel AI Prototype. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Siong Tan , H. Russ , Cecil O. Alford GT-EP: A Novel High-Performance Real-Time Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Higuchi , Tatsumi Furuya , Ken'ichi Handa , Naoto Takahashi , Hiroyasu Nishiyama , Akio Kokubu IXM2: A Parallel Associative Processor. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Kaeli , Philip G. Emma Branch History Table Prediction of Moving Target Branches due to Subroutine Returns. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander C. Klaiber , Henry M. Levy An Architecture for Software-Controlled Data Prefetching. [Citation Graph (1, 0)][DBLP ] Conf ] John W. C. Fu , Janak H. Patel Data Prefetching in Multiprocessor Vector Cache Memories. [Citation Graph (1, 0)][DBLP ] Conf ] David T. Harper III Reducing Memory Contention in Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau Pseudo-Randomly Interleaved Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Li , Karin Petersen Evaluation of Memory System Extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick W. Dowd High Performance Interprocessor Communication through Optical Wavelength Division Multiple Access Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Landin , Erik Hagersten , Seif Haridi Race-Free Interconnection Networks and Multiprocessor Consistency. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaola Lin , Lionel M. Ni Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Arvin Park Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. [Citation Graph (0, 0)][DBLP ] Conf ] Kunle Olukotun , Trevor N. Mudge , Richard B. Brown Implementing a Cache for a High-Performance GaAs Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Paul T. Hulina , Lee D. Coraor , Dhamir N. Mannai Classification and Performance Evaluation of Instruction Buffering Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Masaitsu Nakajima , Hiraku Nakano , Yasuhiro Nakakura , Tadahiro Yoshida , Yoshiyuki Goi , Yuji Nakai , Reiji Segawa , Takeshi Kishida , Hiroshi Kadota OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Vajapeyam , Gurindar S. Sohi , Wei-Chung Hsu An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. [Citation Graph (0, 0)][DBLP ] Conf ] Chriss Stephens , Bryce Cogswell , John Heinlein , Gregory Palmer , John Paul Shen Instruction Level Profiling and Evaluation of the IBM/6000. [Citation Graph (0, 0)][DBLP ] Conf ] Robert T. Dimpsey , Ravishankar K. Iyer Performance Prediction and Tuning on a Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] C. W. Oehlrich , Andreas Quick Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event Traces. [Citation Graph (0, 0)][DBLP ] Conf ] Smaragda Konstantinidou , Lawrence Snyder Chaos Router: Architecture and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Shridhar B. Shukla , Dharma P. Agrawal Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sarita V. Adve , Mark D. Hill , Barton P. Miller , Robert H. B. Netzer Detecting Data Races on Weak Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eric J. Koldinger , Susan J. Eggers , Henry M. Levy On the Validity of Trace-Driven Simulation for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Anoop Gupta , John L. Hennessy , Kourosh Gharachorloo , Todd C. Mowry , Wolf-Dietrich Weber Comparative Evaluation of Latency Reducing and Tolerating Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butler , Tse-Yu Yeh , Yale N. Patt , Mitch Alsup , Hunter Scales , Michael Shebanow Single Instruction Stream Parallelism is Greater Than Two. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Melvin , Yale N. Patt Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sarita V. Adve , Vikram S. Adve , Mark D. Hill , Mary K. Vernon Comparison of Hardware and Software Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Simoni , Mark Horowitz Modeling the Performance of Limited Pointers Directories for Cache Coherence. [Citation Graph (0, 0)][DBLP ] Conf ] Donna J. Quammen , D. Richard Miller Flexible Register Management for Sequential Programs. [Citation Graph (0, 0)][DBLP ] Conf ] David G. Bradlee , Susan J. Eggers , Robert R. Henry The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory M. Papadopoulos , Kenneth R. Traub Multithreading: A Revisionist View of Dataflow Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh Multi-Threaded Vectorization. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Andrew R. Pleszkun Strategies for Achieving Improved Processor Throughput. [Citation Graph (0, 0)][DBLP ] Conf ] Toyohiko Kagimasa , Kikuo Takahashi , Toshiaki Mori , Seiichi Yoshizumi Adaptive Storage Management for Very Large Virtual/Real Storage Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Judith S. Hall , Paul T. Robinson Virtualizing the VAX Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Janaki Akella , Daniel P. Siewiorek Modeling and Measurement of the Impact of Input/Output on System Performance. [Citation Graph (0, 0)][DBLP ] Conf ] 