Conferences in DBLP
Viktor K. Prasanna , Cauligi S. Raghavendra Array Processor with Multiple Broadcasting. [Citation Graph (0, 0)][DBLP ] Conf ] G. Wolf , J. Robert Jump Matrix Multiplication in an Interleaved Array Processing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] James R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young PIPE: A VLSI Decoupled Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Y.-T. Hsu , Joseph T. Rahmeh , Edward S. Davidson , Jacob A. Abraham TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Smith , Andrew R. Pleszkun Implementation of Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Hasegawa , Yoshiharu Shigei High-Speed Top-of-Stack Scheme for VLSI Processor: a Management Algorithm and Its Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Y. Hitchcock III , Brinkley Sprunt Analyzing Multiple Register Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Jay Smith Cache Evaluation and the Impact of Workload Choice. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Moon Architecture of the Symbolics 3600. [Citation Graph (1, 0)][DBLP ] Conf ] Ashwin Ram , Janak H. Patel Parallel Garbage Collection Without Synchronization Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Gurindar S. Sohi , Edward S. Davidson , Janak H. Patel An Efficient LISP-Execution Architecture with a New Representation for List Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Taisuke Boku , Tomohiro Kudoh , Hideo Aiso (SM)²-II: A New Version of the Sparse Matrix Solving Machine. [Citation Graph (0, 0)][DBLP ] Conf ] John F. Beetem , Monty Denneau , Don Weingarten The GF11 Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Bradley Warren Smith , Howard Jay Siegel Models for Use in the Design of Macro-Pipelined Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Edler , Allan Gottlieb , Clyde P. Kruskal , Kevin P. McAuliffe , Larry Rudolph , Marc Snir , Patricia J. Teller , James Wilson Issues Related to MIMD Shared-memory Computers: The NYU Ultracomputer Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Roland N. Ibbett , P. C. Capon , Nigel P. Topham MU6V: A Parallel Vector Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen F. Lundstrom A Decentralized Control, Highly Concurrent Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Dally , James T. Kajiya An Object Oriented Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Edward F. Gehringer , James Leslie Keedy Tagged Architecture: How Compelling Are its Advantages? [Citation Graph (0, 0)][DBLP ] Conf ] S. Nanba , N. Ohno , H. Kubo , H. Morisue , T. Ohshima , H. Yamagishi VM/4: ACOS-4 Virtual Machine Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Tep P. Dobry , Alvin M. Despain , Yale N. Patt Performance Studies of a Prolog Machine Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ryosei Nakazaki , Akihiko Konagaya , Shinichi Habata , Hideo Shimazu , Mamoru Umemura , Masahiro Yamamoto , Minoru Yokota , Takashi Chikayama Design of a High-speed Prolog Machine (HPM). [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo A Hardware Unification Unit: Design and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas Matelan The FLEX/32 Multicomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Dick Naedel Closely Coupled Asynchronous Hierarchical and Parallel Processing in an Open Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Savage Parallel Processing as a Language Design Problem. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Rodgers Improvements in Multiprocessor System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Peter B. Mark The Sequoia Computer: A Fault-Tolerant Tightly-Coupled Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Elliot Nestle , Armond Inselberg The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Horst , Timothy C. K. Chou An Architecture for High Volume Transaction Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeo Kamiya , Kazuhide Iwata , Hiroshi Sakai , Susumu Matsuda , Shigeki Shibayama , Kunio Murakami A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Dik Lun Lee A Distributed Multiple-Response Resolver for Value-Ordered Retrieval. [Citation Graph (1, 0)][DBLP ] Conf ] John Feo , Roy M. Jenevein , James C. Browne Dynamic, Distributed Resource Configuration on SW-Banyans. [Citation Graph (0, 0)][DBLP ] Conf ] Randy H. Katz , Susan J. Eggers , David A. Wood , C. L. Perkins , R. G. Sheldon Implementing A Cache Consistency Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Li , Walid A. Abu-Sufah A Technique for Reducing Synchronization Overhead in Large Scale Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Whitby-Strevens The Transputer. [Citation Graph (0, 0)][DBLP ] Conf ] Ali R. Hurson , Behrooz Shirazi A Systolic Multiplier Unit and Its VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rami G. Melhem A Language for the Simulation of Systolic Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Y. H. Chuang , Guo He A Versatile Systolic Array for Matrix Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Rex W. Vedder , Dennis Finn The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth R. Traub An Abstract Parallel Graph Reduction Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Bruno R. Preiss , V. Carl Hamacher Data Flow on a Queue Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Luc Gaudiot Methods for Handling Structures in Data-Flow Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Maheswara R. Samatham , Dhiraj K. Pradhan The de Bruijn Multiprocessor Network: A Versatile Sorting Network. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng , Pen-Chung Yew , Chuan-Qi Zhu Fault-Tolerant Scheme for Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay P. Kumar , Sudhakar M. Reddy Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Nathaniel J. Davis IV , Howard Jay Siegel The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Dalibor F. Vrsalovic , Edward F. Gehringer , Zary Segall , Daniel P. Siewiorek The Influence of Parallel Decomposition Strategies on the Performance of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Walid A. Abu-Sufah , Alex Y. Kwok Performance Prediction Tools for Cedar: A Multiprocessor Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Llabería , Mateo Valero , Enrique Herrada Lillo , Jesús Labarta Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. [Citation Graph (0, 0)][DBLP ] Conf ] John Sanguinetti , B. Kumar Performance of a Message-Based Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] 