Conferences in DBLP
Kenneth J. Thurber A Pragmatic View of Distributed Processing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Data Flow Languages and Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce W. Arden , Ran Ginosar MP/C: A Multiprocessor/Computer Architecture. [Citation Graph (1, 0)][DBLP ] Conf ] Dharma P. Agrawal A Pipelined Pseudoparallel System Architecture for Motion Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Hobson Structured Machine Design: An Ongoing Experiement. [Citation Graph (0, 0)][DBLP ] Conf ] R. Jenevien , Doug DeGroot , G. Jack Lipovski A Hardware Support Mechanism for Scheduling Resources in a Parallel Machine Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Faye A. Briggs , Michel Dubois , Kai Hwang Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS. [Citation Graph (0, 0)][DBLP ] Conf ] David Kroft Lockup-Free Instruction Fetch/Prefetch Cache Organization. [Citation Graph (0, 0)][DBLP ] Conf ] Wei C. Yen , King-sun Fu Analysis of Multiprocessor Cache Organizations with Alternative Main Memory Update Policies. [Citation Graph (0, 0)][DBLP ] Conf ] W. L. Bain Jr. , S. R. Ahuja Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Smith A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Arpad Gallo , Richard P. Wilder Performance Measurement of Data Communication Systems with Emphasis on Open System Interconnections (OSI). [Citation Graph (0, 0)][DBLP ] Conf ] G. W. Geitz , E. J. Schmitter BFS-Realization of a Fault-Tolerant Architecuture. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Maekawa Optimal Processor Interconnection Topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dubois , Faye A. Briggs Efficient Interprocessor Communications for MIMD Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan D. Ackland , Neil Weste , David J. Burr An Integrated Multiprocessing Array for Time Warp Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Norton Greenfeld Jericho: A Professional's Personal Computer System. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce W. Arden , Ran Ginosar A Single-Relation Module for a Data Base Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin W. Wah , Y. W. Eva Ma MANIP - A Parallel Computer System for Implementing Branch and Bound Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] P. I. Georgiadis , Mike P. Papazoglou , D. G. Maritsas Towards a Parallel SIMULA Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Philip C. Treleaven , Richard P. Hopkins Decentralized Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind V. Kathail A Multiprocessor Data Flow Machine that Supports Generalized Procedures. [Citation Graph (0, 0)][DBLP ] Conf ] Vason P. Srini An Architecture for Extended Abstract Data Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Forbes J. Burkowski A Multi-User Data Flow Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] M. E. Houdek , F. G. Soltis , R. L. Hoffman IBM System/38 Support for Capability-Based Addressing. [Citation Graph (0, 0)][DBLP ] Conf ] P. Xia , X. Fang , Y. Wang , G. Wang , Y. Liu , C. Li , C. Lin , W. Zhan , Q. Sun An Array Processor for Petroleum Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] K. E. MacKenzie On Refuting the Creation Theory of Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Thornton Heterogeneous Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Souza , Edward E. Balkovich Impact of Hardware Interconnection Structures on the Performance of Decentralized Software. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Hasegawa , Tadao Nakamura , Yoshiharu Shigei Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhir K. Arora , Surya R. Dumpala , K. C. Smith WCRC: An ANSI SPARC Machine Architecture for Data Base Management. [Citation Graph (2, 0)][DBLP ] Conf ] K. Seo , A. Minematsu , Hideo Aiso , Noriyuki Kamibayashi A Look-Ahead Data Staging Architecture for Relational Data Base Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Kiyoki , Katsumi Tanaka , Hideo Aiso , Noriyuki Kamibayashi Design and Evaluation of a Relational Data Base Machine Employing Advanced Data Structures and Algorithms. [Citation Graph (2, 0)][DBLP ] Conf ] Israel Koren A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Patterson , Carlo H. Séquin RISC I: A Reduced Instruction Set VLSI Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Larry L. Kinney , W. Y. Yueh , Walter L. Heimerdinger , Richard R. Ramseyer , J. W. Thomas An Architecture for a VHSIC Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo H. Séquin Doubly Twisted Torus Networks for VLSI Processing Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang K. Giloi , Peter M. Behr An IPC Protocol and Its Hardware Realization for a High-Speed Distributed Multicomputer System. [Citation Graph (0, 0)][DBLP ] Conf ] Z. Chuang-qi , S. Ren-Ben Alignment Network Used for Connecting a Prime Number of Memory Blocks with a Power of 2 of Processing Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Roger M. Needham Design Considerations for a Processing Server. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. McMillen , Howard Jay Siegel Dynamic Rerouting Tag Schemes for the Augmented Data Manipulator Network. [Citation Graph (0, 0)][DBLP ] Conf ] 