Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1973 (conf/isca/73)

1. Dileep Bhandarkar, Samuel H. Fuller
   Markov Chain Models for Analyzing Memory Interference in Multiprocessor Computer Systems. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:1-6 [Conf]
   
2. George A. Anderson
   Interconnecting A Distibuted Processor System for Avionics. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:11-16 [Conf]
   
3. L. Rodney Goke, G. Jack Lipovski
   Banyan Networks for Partitioning Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:21-28 [Conf]
   
4. Harry F. Jordan, Burton J. Smith
   Structure of Digital System Description Languages. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:31-34 [Conf]
   
5. John A. N. Lee
   VDL - A Definitional System for All Levels. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:41-48 [Conf]
   
6. Charles H. Radoy, George P. Copeland, G. Jack Lipovski
   A Methodology for Parallel Processing Design Tradeoffs. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:51-56 [Conf]
   
7. S. F. Reddaway
   DAP - A Distributed Array Processor. [Citation Graph (1, 0)][DBLP]
   ISCA, 1973, pp:61-65 [Conf]
   
8. Peter M. Kogge
   Maximal Rate Pipelined Solutions to Recurrance Problems. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:71-76 [Conf]
   
9. Michael J. Flynn, Tilak Agerwala
   Comments on Capabilities, Limitations and Correctness of Petri Nets. [Citation Graph (0, 0)][DBLP]
   ISCA, 1973, pp:81-86 [Conf]
   
10. Wayne E. Omohundro, James H. Tracey
    Flowware - A Flow Charting Procedure to Describe Digital Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:91-97 [Conf]
    
11. Mario Barbacci, Daniel P. Siewiorek
    Automated Exploration of the Design Space for Register Transfer (RT) Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:101-106 [Conf]
    
12. T. A. Laliotis
    Implementation Aspects of the Symbol Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:111-115 [Conf]
    
13. George P. Copeland, G. Jack Lipovski, Stanley Y. W. Su
    The Architecture of CASSM: A Cellular System for Non-numeric Processing. [Citation Graph (6, 0)][DBLP]
    ISCA, 1973, pp:121-128 [Conf]
    
14. John M. Hemphill, Stephen A. Szygenda
    Deriving Design Guidelines for Diagnosable Computer Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:131-135 [Conf]
    
15. Behrooz Parhami, Algirdas Avizienis
    Design of Fault-Tolerant Associative Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:141-145 [Conf]
    
16. Martin A. Fischler, Oscar Firschein
    A Fault Tolerant Multiprocessor Architecture for Real Time Control Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:151-157 [Conf]
    
17. G. Jack Lipovski
    A Varistructured Fail-Soft Cellular Computer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:161-165 [Conf]
    
18. Jean G. Vaucher, Christian Rey
    A Hardware Laboratory for Computer Architecture Research. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:171-175 [Conf]
    
19. Peter J. Knoke
    Simulation Exercises for Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:181-185 [Conf]
    
20. M. E. Sloan
    Computer Architecture Courses in Electrical Engineering Departments. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:191-195 [Conf]
    
21. Reiner W. Hartenstein
    Increasing Hardware Complexity - A Challenge to Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:201-206 [Conf]
    
22. George Rossmann
    Review of the Workshop on Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:211-214 [Conf]
    
23. Richard Cooper
    Micromodules: Microprogrammable Building Blocks for Hardware Development. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:221-226 [Conf]
    
24. Samuel H. Fuller, Daniel P. Siewiorek, R. J. Swan
    Computer Modules: An Architecture for Large Digital Modules. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:231-237 [Conf]
    
25. Rodnay Zaks
    Microprogrammed Architecture for Front End Processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:241-246 [Conf]
    
26. Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung
    Design of a Fully Variable - Length Structured Minicomputer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:251-255 [Conf]
    
27. Orin E. Marvel
    HAPPE Honeywell Associative Parallel Processing Ensemble. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:261-267 [Conf]
    
28. Marlo R. Schaffner
    A Computer Architecture and its Programming Language. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:271-277 [Conf]