Conferences in DBLP
J. Gregory Steffan , Christopher B. Colohan , Antonia Zhai , Todd C. Mowry A scalable approach to thread-level speculation. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo H. Cintra , José F. Martínez , Josep Torrellas Architectural support for scalable speculative parallelization in shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Steven K. Reinhardt , Shubhendu S. Mukherjee Transient fault detection via simultaneous multithreading. [Citation Graph (0, 0)][DBLP ] Conf ] Quinn Jacobson , James E. Smith Trace preconstruction. [Citation Graph (0, 0)][DBLP ] Conf ] Ryan Rakvic , Bryan Black , John Paul Shen Completion time multiple branch prediction for enhancing trace cache performance. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew C. Merten , Andrew R. Trick , Erik M. Nystrom , Ronald D. Barnes , Wen-mei W. Hwu A hardware mechanism for dynamic extraction and relayout of program hot spots. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Oskin , Frederic T. Chong , Matthew K. Farrens HLS: combining statistical and symbolic simulation to guide microprocessor designs. [Citation Graph (0, 0)][DBLP ] Conf ] David Brooks , Vivek Tiwari , Margaret Martonosi Wattch: a framework for architectural-level power analysis and optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , Hyun Suk Kim , Wu Ye Energy-driven integrated hardware-software optimizations using SimplePower. [Citation Graph (0, 0)][DBLP ] Conf ] Erik G. Hallnor , Steven K. Reinhardt A fully associative software-managed cache design. [Citation Graph (0, 0)][DBLP ] Conf ] Ashley Saulsbury , Fredrik Dahlgren , Per Stenström Recency-based TLB preloading. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Rixner , William J. Dally , Ujval J. Kapasi , Peter R. Mattson , John D. Owens Memory access scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] An-Chow Lai , Babak Falsafi Selective, accurate, and timely self-invalidation using last-touch prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Norman Margolus An embedded DRAM architecture for large-scale spatial-lattice computations. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Mai , Tim Paaske , Nuwan Jayasena , Ron Ho , William J. Dally , Mark Horowitz Smart Memories: a modular reconfigurable architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Craig B. Zilles , Gurindar S. Sohi Understanding the backward slices of performance degrading instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin M. Lepak , Mikko H. Lipasti On the value locality of store instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Zarka Cvetanovic , Richard E. Kessler Performance analysis of the Alpha 21264-based Compaq ES40 system. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Faraboschi , Geoffrey Brown , Joseph A. Fisher , Giuseppe Desoli , Fred Homewood Lx: a technology platform for customizable VLIW embedded processing. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathy Ranganathan , Sarita V. Adve , Norman P. Jouppi Reconfigurable caches and their application to media processing. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi Alex Ye , Andreas Moshovos , Scott Hauck , Prithviraj Banerjee CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP ] Conf ] Dana S. Henry , Bradley C. Kuszmaul , Gabriel H. Loh , Rahul Sami Circuits for wide-window superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Agarwal , M. S. Hrishikesh , Stephen W. Keckler , Doug Burger Clock rate versus IPC: the end of the road for conventional microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Smith , Greg Faanes , Rabin A. Sugumar Vector instruction set support for conditional operations. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan C. Chou , John Paul Shen Instruction path coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Luiz André Barroso , Kourosh Gharachorloo , Robert McNamara , Andreas Nowatzyk , Shaz Qadeer , Barton Sano , Scott Smith , Robert Stets , Ben Verghese Piranha: a scalable architecture based on single-chip multiprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Radhakrishnan , Deependra Talla , Lizy Kurian John Allowing for ILP in an embedded Java processor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Bekerman , Adi Yoaz , Freddy Gabbay , Stéphan Jourdan , Maxim Kalaev , Ronny Ronen Early load address resolution via register tracking. [Citation Graph (0, 0)][DBLP ] Conf ] José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P. Topham Multiple-banked register file architectures. [Citation Graph (0, 0)][DBLP ] Conf ] 