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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2000 (conf/isca/2000)

  1. J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry
    A scalable approach to thread-level speculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:1-12 [Conf]
  2. Marcelo H. Cintra, José F. Martínez, Josep Torrellas
    Architectural support for scalable speculative parallelization in shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:13-24 [Conf]
  3. Steven K. Reinhardt, Shubhendu S. Mukherjee
    Transient fault detection via simultaneous multithreading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:25-36 [Conf]
  4. Quinn Jacobson, James E. Smith
    Trace preconstruction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:37-46 [Conf]
  5. Ryan Rakvic, Bryan Black, John Paul Shen
    Completion time multiple branch prediction for enhancing trace cache performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:47-58 [Conf]
  6. Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu
    A hardware mechanism for dynamic extraction and relayout of program hot spots. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:59-70 [Conf]
  7. Mark Oskin, Frederic T. Chong, Matthew K. Farrens
    HLS: combining statistical and symbolic simulation to guide microprocessor designs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:71-82 [Conf]
  8. David Brooks, Vivek Tiwari, Margaret Martonosi
    Wattch: a framework for architectural-level power analysis and optimizations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:83-94 [Conf]
  9. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye
    Energy-driven integrated hardware-software optimizations using SimplePower. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:95-106 [Conf]
  10. Erik G. Hallnor, Steven K. Reinhardt
    A fully associative software-managed cache design. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:107-116 [Conf]
  11. Ashley Saulsbury, Fredrik Dahlgren, Per Stenström
    Recency-based TLB preloading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:117-127 [Conf]
  12. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens
    Memory access scheduling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:128-138 [Conf]
  13. An-Chow Lai, Babak Falsafi
    Selective, accurate, and timely self-invalidation using last-touch prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:139-148 [Conf]
  14. Norman Margolus
    An embedded DRAM architecture for large-scale spatial-lattice computations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:149-160 [Conf]
  15. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
    Smart Memories: a modular reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:161-171 [Conf]
  16. Craig B. Zilles, Gurindar S. Sohi
    Understanding the backward slices of performance degrading instructions. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:172-181 [Conf]
  17. Kevin M. Lepak, Mikko H. Lipasti
    On the value locality of store instructions. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:182-191 [Conf]
  18. Zarka Cvetanovic, Richard E. Kessler
    Performance analysis of the Alpha 21264-based Compaq ES40 system. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:192-202 [Conf]
  19. Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred Homewood
    Lx: a technology platform for customizable VLIW embedded processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:203-213 [Conf]
  20. Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
    Reconfigurable caches and their application to media processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:214-224 [Conf]
  21. Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
    CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:225-235 [Conf]
  22. Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami
    Circuits for wide-window superscalar processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:236-247 [Conf]
  23. Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger
    Clock rate versus IPC: the end of the road for conventional microarchitectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:248-259 [Conf]
  24. James E. Smith, Greg Faanes, Rabin A. Sugumar
    Vector instruction set support for conditional operations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:260-269 [Conf]
  25. Yuan C. Chou, John Paul Shen
    Instruction path coprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:270-281 [Conf]
  26. Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
    Piranha: a scalable architecture based on single-chip multiprocessing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:282-293 [Conf]
  27. Ramesh Radhakrishnan, Deependra Talla, Lizy Kurian John
    Allowing for ILP in an embedded Java processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:294-305 [Conf]
  28. Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
    Early load address resolution via register tracking. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:306-315 [Conf]
  29. José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
    Multiple-banked register file architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:316-325 [Conf]
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