The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1986 (conf/isca/86)

  1. Haruo Yokota, Hidenori Itoh
    A Model and an Architecture for a Relational Knowledge Base. [Citation Graph (4, 0)][DBLP]
    ISCA, 1986, pp:2-9 [Conf]
  2. Makoto Amamiya, Masaru Takesue, Ryuzo Hasegawa, Hirohide Mikami
    Implementation and Evaluation of a List-Processing-Oriented Data Flow Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:10-19 [Conf]
  3. K. Takahashi, H. Yamada, H. Nagai, K. Matsumi
    A New String Search Hardware Architecture for VLSI. [Citation Graph (2, 0)][DBLP]
    ISCA, 1986, pp:20-27 [Conf]
  4. Anoop Gupta, Charles Forgy, Allen Newell, Robert G. Wedig
    Parallel Algorithms and Architectures for Rule-Based Systems. [Citation Graph (5, 0)][DBLP]
    ISCA, 1986, pp:28-37 [Conf]
  5. Robert H. Halstead Jr., Thomas L. Anderson, Randy B. Osborne, Thomas L. Sterling
    Concert: Design of a Multiprocessor Development System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:40-48 [Conf]
  6. H. T. Kung
    Memory Requirements for Balanced Computer Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:49-54 [Conf]
  7. Yang-Chang Hong, Thomas H. Payne, Le Baron O. Ferguson
    Graph Allocation in Static Dataflow Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:55-64 [Conf]
  8. Prathima Agrawal, Rakesh Agrawal
    Software Implementation of a Recursive Fault Tolerance Algorithm on a Network of Computers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:65-72 [Conf]
  9. Tohru Nojiri, Shumpei Kawasaki, Kousuke Sakoda
    Microprogrammable Processor for Object-Oriented Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:74-81 [Conf]
  10. Shreekant S. Thakkar, William E. Hostmann
    An Instruction Fetch Unit for a Graph Reduction Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:82-91 [Conf]
  11. Edward F. Gehringer, Robert P. Colwell
    Fast Object-Oriented Procedure Calls: Lessons from the Intel 432. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:92-101 [Conf]
  12. Daniel M. Dias, Balakrishna R. Iyer, Philip S. Yu
    On Coupling Many Small Systems for Transaction Processing. [Citation Graph (1, 0)][DBLP]
    ISCA, 1986, pp:104-110 [Conf]
  13. Mohammad Malkawi, Janak H. Patel
    Performance Measurement of Paging Behavior in Multiprogramming Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:111-118 [Conf]
  14. Anant Agarwal, Richard L. Sites, Mark Horowitz
    ATUM: A New Technique for Capturing Address Traces Using Microcode. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:119-127 [Conf]
  15. Michael J. Wise
    Experimenting With EPILOG: Some Results and Preliminary Conclusions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:130-139 [Conf]
  16. Yasuro Shobatake, Hideo Aiso
    A Unification Processor Based on a Uniformly Structured Cellular Hardware. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:140-148 [Conf]
  17. Noriyoshi Ito, Masatoshi Sato, Eiji Kuno, Kazuaki Rokusawa
    The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:149-156 [Conf]
  18. André Seznec
    An Efficient Routing Control Unit for the SIGMA Network E(4). [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:158-168 [Conf]
  19. Jean-Daniel Nicoud, K. Skala
    REYSM, A High Performance, Low Power Multi-Microprocessor Bus. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:169-174 [Conf]
  20. Kyungsook Y. Lee, Wael Hegazy
    The Extra Stage Gamma Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:175-182 [Conf]
  21. Masanobu Yuhara, Akira Hattori, Masashi Niwa, Mitsuhiro Kishimoto, Hiromu Hayashi
    Evaluation of the FACOM ALPHA Lisp Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:184-190 [Conf]
  22. Andrew R. Pleszkun, Matthew Thazhuthaveetil
    An Architecture for Efficient Lisp List Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:191-198 [Conf]
  23. Toshiyuki Nakata, Nobuhiko Koike
    A Functional Level Simulation Engine of MAN-YO: A Special Purpose Parallel Machine for Logic Design Automation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:202-208 [Conf]
  24. Edward H. Frank
    Exploiting Parallelism in a Switch-Level Simulation Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:209-215 [Conf]
  25. Thomas S. Anantharaman, Roberto Bisiani
    A Hardware Accelerator for Speech Recognition Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:216-223 [Conf]
  26. Toshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi
    Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:226-234 [Conf]
  27. John Sargeant, Chris C. Kirkham
    Stored Data Structures on the Manchester Dataflow Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:235-242 [Conf]
  28. K. Kawakami, John R. Gurd
    A Salable Dataflow Structure Store. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:243-250 [Conf]
  29. Makoto Hasegawa, Yoshiharu Shigei
    AT2=O(N log4 N), T=O(log N) Fast Fourier Transform in a Light Connected 3-Dimensional VLSI. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:252-260 [Conf]
  30. Krzysztof Sapiecha, R. Jarocki
    Modular Architecture for High Performance Implementation of FFT Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:261-270 [Conf]
  31. Juan J. Navarro, José M. Llabería, Mateo Valero
    Computing Size-Independent Matrix Problems on Systolic Array Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:271-278 [Conf]
  32. Shinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara
    A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:280-289 [Conf]
  33. Masaharu Hirayama
    VLSI Oriented Asynchronous Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:290-296 [Conf]
  34. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:297-306 [Conf]
  35. Kenji Onaga, Takahiro Takechi
    On Design of Rotary Array Communication and Wavefront-Driven Algorithms for Solving Large-Scale Band-Limited Matrix Equations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:308-315 [Conf]
  36. Leonard M. Napolitano Jr.
    A Computer Architecture for Dynamic Finite Element Analysis. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:316-323 [Conf]
  37. David T. Harper III, J. Robert Jump
    Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:324-328 [Conf]
  38. Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima
    Pseudo MIMD Array Processor - AAP2. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:330-337 [Conf]
  39. Allan L. Fisher
    Scan Line Array Processors for Image Computation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:338-345 [Conf]
  40. Marco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb
    Warp Architecture and Implementation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:346-356 [Conf]
  41. David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson
    An In-Cache Address Translation Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:358-365 [Conf]
  42. David R. Cheriton, Gert Slavenburg, Patrick D. Boyle
    Software-Controlled Caches in the VMP Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:366-374 [Conf]
  43. James R. Goodman, Wei-Chung Hsu
    On the Use of Registers vs. Cache to Minimize Memory Traffic. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:375-383 [Conf]
  44. Peter Y.-T. Hsu, Edward S. Davidson
    Highly Concurrent Scalar Processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:386-395 [Conf]
  45. Scott McFarling, John L. Hennessy
    Reducing the Cost of Branches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:396-403 [Conf]
  46. Steven R. Kunkel, James E. Smith
    Optimal Pipelining in Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:404-411 [Conf]
  47. Paul Sweazey, Alan Jay Smith
    A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:414-423 [Conf]
  48. Philip Bitar, Alvin M. Despain
    Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:424-433 [Conf]
  49. Michel Dubois, Christoph Scheurich, Faye A. Briggs
    Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:434-442 [Conf]
  50. George S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn
    Evaluation of the SPUR Lisp Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:444-452 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002