Conferences in DBLP
Jack B. Dennis , G. Andrew Boughton , Clement K. C. Leung Building Blocks for Data Flow Prototypes. [Citation Graph (0, 0)][DBLP ] Conf ] Edward S. Davidson A Multiple Stream Microprocessor Prototype System: AMP-1. [Citation Graph (0, 0)][DBLP ] Conf ] F. André , Jean-Pierre Banâtre , H. Leroy , G. Paget , Florimond Ployette , Jean-Paul Routeau Kensur: An Architecture Oriented Towards Programming Languages Translation. [Citation Graph (0, 0)][DBLP ] Conf ] Jon G. Kuhl , Sudhakar M. Reddy Distributed Fault-Tolerance For Large Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslaw Malek A Comparison Connection Assignment for Diagnosis of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Karl-Erwin Großpietsch , Jörg Kaiser , Edgar Nett A Concept for Test and Reconfiguration of a Fault-Tolerant VLSI Processor System. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Paul Brassard , Jan Gecsei Path Building in Cellular Partitioning Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. McMillen , Howard Jay Siegel MIMD Machine Communication Using the Augmented Data Manipulator Network. [Citation Graph (0, 0)][DBLP ] Conf ] John Paul Shen , John P. Hayes Fault Tolerance of a Class of Connecting Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Edward G. Coffman Jr. , Kimming So On the Comparison Between Single and Multiple Processor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] V. Carl Hamacher , Gerald S. Shedler Performance of a Collision-Free Local Bus Network Having Asynchronous Distributed Control. [Citation Graph (0, 0)][DBLP ] Conf ] Wlodzimierz M. Zuberek Timed Petri Nets and Preliminary Performance Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Ditzel , David A. Patterson Retrospective on High-Level Language Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Paul Sansonnet , Michel Castan , Christian Percebois M3L: A List-Directed Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Hibino A Practical Parallel Garbage Collection Algorithm and Its Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Philip C. Trevleaven , Geoffrey F. Mole A Multi-Processor Reduction Machine for User-Defined Reduction Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Tobias A Single User Multiprocessor Incorporating Processor Manipulation Facilities. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Halstead Jr. , Stephen A. Ward The Munet: A Scalable Decentralized Architecture For Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Butler W. Lampson , Kenneth A. Pier A Processor for a High-Performance Personal Computer. [Citation Graph (0, 0)][DBLP ] Conf ] David B. G. Edwards , Alan E. Knowles , J. V. Woods MU6-G: A New Design to Achieve Mainframe Performance from a Mini-Sized Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Batcher Architecture of a Massively Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] John Palmer The Intel 8087 Numeric Data Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Kuhn Efficient Mapping of Algorthims To Single-Stage Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] David Nassimi A Self-Routing Benes Network. [Citation Graph (0, 0)][DBLP ] Conf ] Hermann von Issendorff , W. Grunewald An Adaptable Network for Functional Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mokhtar Boshra Riad A Combination of Field and Current Access Techniques for Effiecient and Cost-Effective Bubble Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Kishor S. Trivedi Designing Linear Storage Hierarchies so as to Maximize Reliability Subject to Cost and Performance Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhir Ahuja , Charles S. Roberts An Associative/Parallel Processor for Partial Match Retrieval Using Superimposed Codes. [Citation Graph (5, 0)][DBLP ] Conf ] M. D. Ruggiero , Safwat G. Zaky A Microprocessor-Based Virtual Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Jagannathan A Technique for the Architectural Implementation of Software Subsystems. [Citation Graph (0, 0)][DBLP ] Conf ] Viktors Berstis Security and Protection of Data in the IBM System/38. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Garcia Hoffman Hardware Implementation of Communication Protocols: A Formal Approach. [Citation Graph (0, 0)][DBLP ] Conf ] P. Guillier , D. Slosberg An Architecture with Comprehensive Facilities of Inter-Process Synchronization and Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Lougheed , David L. McCubbrey The Cytocomputer: A Practical Pipelined Image Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Constantine Halatsis , Andries van Dam , J. Joosten , M. Letheren Architectural Considerations for a Microprogrammable Emulating Engine Using Bitslices. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Jane Irwin , Don Heller Online Pipeline Systems for Recursive Numeric Computations. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Foster , H. T. Kung Design of Special-Purpose VLSI Chips: Example and Opinions. [Citation Graph (0, 0)][DBLP ] Conf ] Anshul Kumar , P. C. P. Bhatt A Structured Language for CAD of Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hercksen , Rainer Klar , Wolfgang Kleinöder Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Tokoro , Klichiro Tamaru , Masaaki Mizuno , Masao Hori A High-Level Multi-Lingual Multiprocessor KMP. [Citation Graph (0, 0)][DBLP ] Conf ] 