The SCEAS System
Navigation Menu

Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1994 (conf/isca/94)

  1. Brad Calder, Dirk Grunwald
    Fast and Accurate Instruction Fetch and Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:2-11 [Conf]
  2. Adam R. Talcott, Wayne Yamamoto, Mauricio J. Serrano, Roger C. Wood, Mario Nemirovsky
    The Impact of Unresolved Branches on Branch Prediction Scheme Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:12-21 [Conf]
  3. Subbarao Palacharla, Richard E. Kessler
    Evaluating Stream Buffers as a Secondary Cache Replacement. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:24-33 [Conf]
  4. Norman P. Jouppi, Steven J. E. Wilton
    Tradeoffs in Two-Level On-Chip Caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:34-45 [Conf]
  5. Ashok Singhal, Aaron J. Goldberg
    Architectural Support for Performance Tuning: A Case Study on the SPARCcenter2000. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:48-59 [Conf]
  6. Zarka Cvetanovic, Dileep Bhandarkar
    Characterization of Alpha AXP Performance Using TP and SPEC Workloads. [Citation Graph (2, 0)][DBLP]
    ISCA, 1994, pp:60-70 [Conf]
  7. Chitra Natarajan, Sanjay Sharma, Ravishankar K. Iyer
    Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:71-80 [Conf]
  8. Truman Joe, John L. Hennessy
    Evaluating the Memory Overhead Required for COMA Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:82-93 [Conf]
  9. Alexander C. Klaiber, Henry M. Levy
    A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:94-105 [Conf]
  10. Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, Honghui Lu, Ramakrishnan Rajamony, Willy Zwaenepoel
    Software Versus Hardware Shared-Memory Implementation: A Case Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:106-117 [Conf]
  11. Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Guarded Executing and Branch Prediction in Dynamic ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:120-129 [Conf]
  12. Ching-Long Su, Alvin M. Despain
    Branch with Masked Squashing in Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:130-140 [Conf]
  13. Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg
    Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. [Citation Graph (1, 0)][DBLP]
    ISCA, 1994, pp:142-153 [Conf]
  14. Peter Steenkiste, Michael Hemy, Todd W. Mummert, Brian Zill
    Architecture and Evaluation of High-Speed Networking Subsystem for Distributed-Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:154-163 [Conf]
  15. Basem A. Nayfeh, Kunle Olukotun
    Exploring the Design Space for a Shared-Cache Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:166-175 [Conf]
  16. Radhika Thekkath, Susan J. Eggers
    Impact of Sharing-Based Thread Placement on Multithreaded Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:176-186 [Conf]
  17. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Combined Performance Gains of Simple Cache Protocol Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:187-197 [Conf]
  18. Andrew S. Huang, Gert Slavenburg, John Paul Shen
    Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:200-210 [Conf]
  19. Keith I. Farkas, Norman P. Jouppi
    Complexity/Performance Tradeoffs with Non-Blocking Loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:211-222 [Conf]
  20. Tien-Fu Chen, Jean-Loup Baer
    A Performance Study of Software and Hardware Data Prefetching Schemes. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:223-232 [Conf]
  21. Ann L. Drapeau, Ken Shirriff, John H. Hartman, Ethan L. Miller, Srinivasan Seshan, Randy H. Katz, Ken Lutz, David A. Patterson, Edward K. Lee, Peter M. Chen, Garth A. Gibson
    RAID-II: A High-Bandwidth Network File Server. [Citation Graph (2, 0)][DBLP]
    ISCA, 1994, pp:234-244 [Conf]
  22. Mario Blaum, Jim Brady, Jehoshua Bruck, Jai Menon
    EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID Architectures. [Citation Graph (1, 0)][DBLP]
    ISCA, 1994, pp:245-254 [Conf]
  23. Spencer W. Ng
    Crosshatch Disk Array for Improved Reliability and Performance. [Citation Graph (1, 0)][DBLP]
    ISCA, 1994, pp:255-264 [Conf]
  24. Frederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.
    METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:266-277 [Conf]
  25. James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili
    Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:278-288 [Conf]
  26. Jae H. Kim, Ziqiang Liu, Andrew A. Chien
    Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:289-300 [Conf]
  27. Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
    The Stanford FLASH Multiprocessor. [Citation Graph (2, 0)][DBLP]
    ISCA, 1994, pp:302-313 [Conf]
  28. David Chaiken, Anant Agarwal
    Software-Extended Coherent Shared Memory: Performance and Cost. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:314-324 [Conf]
  29. Steven K. Reinhardt, James R. Larus, David A. Wood
    Tempest and Typhoon: User-Level Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:325-336 [Conf]
  30. Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
    A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:338-347 [Conf]
  31. Chung-Ho Chen, Arun K. Somani
    A Unified Architectural Tradeoff Methodology. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:348-357 [Conf]
  32. David Nagle, Richard Uhlig, Trevor N. Mudge, Stuart Sechrest
    Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:358-369 [Conf]
  33. Russell W. Quong
    Expected I-Cache Miss Rates via the Gap Model. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:372-383 [Conf]
  34. André Seznec
    Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:384-393 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002