Conferences in DBLP
Brad Calder , Dirk Grunwald Fast and Accurate Instruction Fetch and Branch Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Adam R. Talcott , Wayne Yamamoto , Mauricio J. Serrano , Roger C. Wood , Mario Nemirovsky The Impact of Unresolved Branches on Branch Prediction Scheme Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Subbarao Palacharla , Richard E. Kessler Evaluating Stream Buffers as a Secondary Cache Replacement. [Citation Graph (0, 0)][DBLP ] Conf ] Norman P. Jouppi , Steven J. E. Wilton Tradeoffs in Two-Level On-Chip Caching. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Singhal , Aaron J. Goldberg Architectural Support for Performance Tuning: A Case Study on the SPARCcenter2000. [Citation Graph (0, 0)][DBLP ] Conf ] Zarka Cvetanovic , Dileep Bhandarkar Characterization of Alpha AXP Performance Using TP and SPEC Workloads. [Citation Graph (2, 0)][DBLP ] Conf ] Chitra Natarajan , Sanjay Sharma , Ravishankar K. Iyer Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Truman Joe , John L. Hennessy Evaluating the Memory Overhead Required for COMA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander C. Klaiber , Henry M. Levy A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Alan L. Cox , Sandhya Dwarkadas , Peter J. Keleher , Honghui Lu , Ramakrishnan Rajamony , Willy Zwaenepoel Software Versus Hardware Shared-Memory Implementation: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Dionisios N. Pnevmatikatos , Gurindar S. Sohi Guarded Executing and Branch Prediction in Dynamic ILP Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Long Su , Alvin M. Despain Branch with Masked Squashing in Superpipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias A. Blumrich , Kai Li , Richard Alpert , Cezary Dubnicki , Edward W. Felten , Jonathan Sandberg Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. [Citation Graph (1, 0)][DBLP ] Conf ] Peter Steenkiste , Michael Hemy , Todd W. Mummert , Brian Zill Architecture and Evaluation of High-Speed Networking Subsystem for Distributed-Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Basem A. Nayfeh , Kunle Olukotun Exploring the Design Space for a Shared-Cache Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Radhika Thekkath , Susan J. Eggers Impact of Sharing-Based Thread Placement on Multithreaded Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Fredrik Dahlgren , Michel Dubois , Per Stenström Combined Performance Gains of Simple Cache Protocol Extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew S. Huang , Gert Slavenburg , John Paul Shen Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. [Citation Graph (0, 0)][DBLP ] Conf ] Keith I. Farkas , Norman P. Jouppi Complexity/Performance Tradeoffs with Non-Blocking Loads. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Fu Chen , Jean-Loup Baer A Performance Study of Software and Hardware Data Prefetching Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Ann L. Drapeau , Ken Shirriff , John H. Hartman , Ethan L. Miller , Srinivasan Seshan , Randy H. Katz , Ken Lutz , David A. Patterson , Edward K. Lee , Peter M. Chen , Garth A. Gibson RAID-II: A High-Bandwidth Network File Server. [Citation Graph (2, 0)][DBLP ] Conf ] Mario Blaum , Jim Brady , Jehoshua Bruck , Jai Menon EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID Architectures. [Citation Graph (1, 0)][DBLP ] Conf ] Spencer W. Ng Crosshatch Disk Array for Improved Reliability and Performance. [Citation Graph (1, 0)][DBLP ] Conf ] Frederic T. Chong , Henry Minsky , André DeHon , Matthew Becker , Samuel Peretz , Eran Egozy , Thomas F. Knight Jr. METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Allen , Patrick T. Gaughan , David E. Schimmel , Sudhakar Yalamanchili Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Jae H. Kim , Ziqiang Liu , Andrew A. Chien Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Kuskin , David Ofelt , Mark Heinrich , John Heinlein , Richard Simoni , Kourosh Gharachorloo , John Chapin , David Nakahira , Joel Baxter , Mark Horowitz , Anoop Gupta , Mendel Rosenblum , John L. Hennessy The Stanford FLASH Multiprocessor. [Citation Graph (2, 0)][DBLP ] Conf ] David Chaiken , Anant Agarwal Software-Extended Coherent Shared Memory: Performance and Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Steven K. Reinhardt , James R. Larus , David A. Wood Tempest and Typhoon: User-Level Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Gary S. Tyson , Andrew R. Pleszkun A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ho Chen , Arun K. Somani A Unified Architectural Tradeoff Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] David Nagle , Richard Uhlig , Trevor N. Mudge , Stuart Sechrest Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Russell W. Quong Expected I-Cache Miss Rates via the Gap Model. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. [Citation Graph (0, 0)][DBLP ] Conf ] 