Conferences in DBLP
Marius Evers , Po-Yung Chang , Yale N. Patt Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas C. Gloy Cliff Young, J. Bradley Chen, Michael D. Smith: An Analysis of Dynamic Branch Prediction Schemes on System Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart Sechrest , Chih-Chieh Lee , Trevor N. Mudge Correlation and Aliasing in Dynamic Branch Predictors. [Citation Graph (0, 0)][DBLP ] Conf ] Steven K. Reinhardt , Robert W. Pfile , David A. Wood Decoupled Hardware Support for Distributed Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Yeung , John Kubiatowicz , Anant Agarwal MGS: A Multigrain Shared Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Christine Morin , Alain Gefflaut , Michel Banâtre , Anne-Marie Kermarrec COMA: An Opportunity for Building Fault-Tolerant Scalable Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Basem A. Nayfeh , Lance Hammond , Kunle Olukotun Evaluation of Design Alternatives for a Multiprocessor Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Doug Burger , James R. Goodman , Alain Kägi Memory Bandwidth Limitations of Future Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ashley Saulsbury , Fong Pong , Andreas Nowatzyk Missing the Memory Wall: The Case for Processor/Memory Integration. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec Don't Use the Page Number, But a Pointer To It. [Citation Graph (0, 0)][DBLP ] Conf ] Toni Juan , Tomás Lang , Juan J. Navarro The Difference-bit Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Liviu Iftode , Jaswinder Pal Singh , Kai Li Understanding Application Performance on Shared Virtual Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Holt , Jaswinder Pal Singh , John L. Hennessy Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Wilson , Kunle Olukotun , Mendel Rosenblum Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin , Gurindar S. Sohi High-Bandwidth Address Translation for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yiming Hu , Qing Yang DCD - Disk Caching Disk: A New Approach for Boosting I/O Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Maquelin , Guang R. Gao , Herbert H. J. Hum , Kevin B. Theobald , Xinmin Tian Polling Watchdog: Combining Polling and Interrupts for Efficient Message Handling. [Citation Graph (0, 0)][DBLP ] Conf ] Dean M. Tullsen , Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Eickemeyer , Ross E. Johnson , Steven R. Kunkel , Mark S. Squillante , Shiafun Liu Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. [Citation Graph (1, 0)][DBLP ] Conf ] Tetsuya Hara , Hideki Ando , Chikako Nakanishi , Masao Nakaya Performance Comparison of ILP Machines with Cycle Time Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Jae H. Kim , Andrew A. Chien Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-Cost, High-Performance Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer Rexford , John Hall , Kang G. Shin A Router Architecture for Real-Time Point-to-Point Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shubhendu S. Mukherjee , Babak Falsafi , Mark D. Hill , David A. Wood Coherent Network Interfaces for Fine-Grain Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Horowitz , Margaret Martonosi , Todd C. Mowry , Michael D. Smith Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Xia , Josep Torrellas Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. [Citation Graph (0, 0)][DBLP ] Conf ] Lynn Choi , Pen-Chung Yew Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Felten , Richard Alpert , Angelos Bilas , Matthias A. Blumrich , Douglas W. Clark , Stefanos N. Damianakis , Cezary Dubnicki , Liviu Iftode , Kai Li Early Experience with Message-Passing on the SHRIMP Multicomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Lovett , Russell M. Clapp STiNG: A CC-NUMA Computer System for the Commercial Marketplace. [Citation Graph (0, 0)][DBLP ] Conf ] 