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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1996 (conf/isca/96)

  1. Marius Evers, Po-Yung Chang, Yale N. Patt
    Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:3-11 [Conf]
  2. Nicholas C. Gloy
    Cliff Young, J. Bradley Chen, Michael D. Smith: An Analysis of Dynamic Branch Prediction Schemes on System Workloads. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:12-21 [Conf]
  3. Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge
    Correlation and Aliasing in Dynamic Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:22-32 [Conf]
  4. Steven K. Reinhardt, Robert W. Pfile, David A. Wood
    Decoupled Hardware Support for Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:34-43 [Conf]
  5. Donald Yeung, John Kubiatowicz, Anant Agarwal
    MGS: A Multigrain Shared Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:44-55 [Conf]
  6. Christine Morin, Alain Gefflaut, Michel Banâtre, Anne-Marie Kermarrec
    COMA: An Opportunity for Building Fault-Tolerant Scalable Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:56-65 [Conf]
  7. Basem A. Nayfeh, Lance Hammond, Kunle Olukotun
    Evaluation of Design Alternatives for a Multiprocessor Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:67-77 [Conf]
  8. Doug Burger, James R. Goodman, Alain Kägi
    Memory Bandwidth Limitations of Future Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:78-89 [Conf]
  9. Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
    Missing the Memory Wall: The Case for Processor/Memory Integration. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:90-101 [Conf]
  10. André Seznec
    Don't Use the Page Number, But a Pointer To It. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:104-113 [Conf]
  11. Toni Juan, Tomás Lang, Juan J. Navarro
    The Difference-bit Cache. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:114-120 [Conf]
  12. Liviu Iftode, Jaswinder Pal Singh, Kai Li
    Understanding Application Performance on Shared Virtual Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:122-133 [Conf]
  13. Chris Holt, Jaswinder Pal Singh, John L. Hennessy
    Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:134-145 [Conf]
  14. Kenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum
    Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:147-157 [Conf]
  15. Todd M. Austin, Gurindar S. Sohi
    High-Bandwidth Address Translation for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:158-167 [Conf]
  16. Yiming Hu, Qing Yang
    DCD - Disk Caching Disk: A New Approach for Boosting I/O Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:169-178 [Conf]
  17. Olivier Maquelin, Guang R. Gao, Herbert H. J. Hum, Kevin B. Theobald, Xinmin Tian
    Polling Watchdog: Combining Polling and Interrupts for Efficient Message Handling. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:179-188 [Conf]
  18. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
    Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:191-202 [Conf]
  19. Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu
    Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. [Citation Graph (1, 0)][DBLP]
    ISCA, 1996, pp:203-212 [Conf]
  20. Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
    Performance Comparison of ILP Machines with Cycle Time Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:213-224 [Conf]
  21. Jae H. Kim, Andrew A. Chien
    Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-Cost, High-Performance Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:226-236 [Conf]
  22. Jennifer Rexford, John Hall, Kang G. Shin
    A Router Architecture for Real-Time Point-to-Point Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:237-246 [Conf]
  23. Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, David A. Wood
    Coherent Network Interfaces for Fine-Grain Communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:247-258 [Conf]
  24. Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
    Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:260-270 [Conf]
  25. Chun Xia, Josep Torrellas
    Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:271-282 [Conf]
  26. Lynn Choi, Pen-Chung Yew
    Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:283-294 [Conf]
  27. Edward W. Felten, Richard Alpert, Angelos Bilas, Matthias A. Blumrich, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Liviu Iftode, Kai Li
    Early Experience with Message-Passing on the SHRIMP Multicomputer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:296-307 [Conf]
  28. Tom Lovett, Russell M. Clapp
    STiNG: A CC-NUMA Computer System for the Commercial Marketplace. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:308-317 [Conf]
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