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IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2003 (conf/iscas/2003-1)

  1. Yi-Ran Sun, Svante Signell
    Algorithms for nonuniform bandpass sampling in radio receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1-4 [Conf]
  2. Aránzazu Otín, Santiago Celma, Concepción Aldea
    Modeling of accumulation MOS capacitors for high performance analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:5-8 [Conf]
  3. G. Kathiresan, Emmanuel M. Drakakis, Chris Toumazou
    A highly linear front-end based on a logarithmic multiplier-filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:9-12 [Conf]
  4. Antonio J. López-Martín, Alfonso Carlosena, Jaime Ramírez-Angulo
    A novel design technique for very low voltage MOS translinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:13-16 [Conf]
  5. André van Schaik
    A small analog VLSI inner hair cell model. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:17-20 [Conf]
  6. Kai-Sheng Lu
    Some structural conditions under which an RLC network is controllable over F(z). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:21-24 [Conf]
  7. Philipp Häfliger, Håvard Kolle Riis
    A multi-level static memory cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:25-28 [Conf]
  8. Sung-Eun Kim, Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo
    CMOS optical receiver chipset for gigabit Ethernet applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:29-32 [Conf]
  9. Esa Tiiliharju, Kari Halonen
    A biased low-voltage BiCMOS mixer for direct up-conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:33-36 [Conf]
  10. Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao
    A high-resolution and fast-conversion time-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:37-40 [Conf]
  11. S. Khucharoensin, V. Kasemsuwan
    High performance CMOS current-mode precision full-wave rectifier (PFWR). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:41-44 [Conf]
  12. Bo Shi, Lars Sundström
    A time-continuous optimization method for automatic adjustment of gain and phase imbalances in feedforward and LINC transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:45-48 [Conf]
  13. Guangyu Zhang, Pruthvi (Peter) Chaudhari, Michael M. Green
    A BiCMOS 10Gb/s adaptive cable equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:49-52 [Conf]
  14. Erik Sall
    A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:53-56 [Conf]
  15. N. Nastos, Yannis Papananos
    Integrated inductors over MOSFETs - experimental results of a three dimensional integrated structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:57-60 [Conf]
  16. J. Shorb, Xiaoyong Li, David J. Allstot
    A resonant pad for ESD protected narrowband CMOS RF applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:61-64 [Conf]
  17. Mohamed Lamine Tounsi, H. Halheit, Mustapha Chérif-Eddine Yagoub, Abdfelhamid Khodja
    Analysis of shielded planar circuits by a mixed variational-spectral method. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:65-68 [Conf]
  18. Alyssa B. Apsel, Andreas G. Andreou
    A 7 milliwatt 1GBPS CMOS optical receiver for through wafer communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:69-72 [Conf]
  19. Chin-Shan Hsieh, Hong-Yi Huang, Jeng-Dang Juan, Ruey-Nan Yeh
    A high-bandwidth wireless infrared receiver with feedforward offset extractor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:73-76 [Conf]
  20. Alyssa B. Apsel, Andreas G. Andreou
    A 10 milliwatt 2 Gbps CMOS optical receiver for optoelectronic interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:77-80 [Conf]
  21. Elisabetta Chicca, Giacomo Indiveri, Rodney J. Douglas
    An adaptive silicon synapse. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:81-84 [Conf]
  22. Matthias Frey, Hans-Andrea Loeliger, Felix Lustenberger, Patrick Merkli, Patrik Strebel
    Analog-decoder experiments with subthreshold CMOS soft-gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:85-88 [Conf]
  23. Srinivas Kodali, David J. Allstot
    A symmetric miniature 3D inductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:89-92 [Conf]
  24. Srinivas Kodali, Taeik Kim, David J. Allstot
    On-chip inductor structures: a comparative study. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:93-96 [Conf]
  25. Janusz Biernacki, Dariusz Czarkowski
    RF transformer as a directional coupler with arbitrary load. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:97-100 [Conf]
  26. C. K. L. Tam, Gordon W. Roberts
    A DC current measurement circuit for on-chip applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:101-104 [Conf]
  27. Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta
    A digitally skew correctable multi-phase clock generator using a master-slave DLL. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:105-108 [Conf]
  28. J. Yoo, E. Lee, Earl E. Swartzlander Jr.
    A self-testing method for the pipelined A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:109-112 [Conf]
  29. Igor M. Filanovsky, P. N. Matkhanov
    Synthesis of a pulse-forming reactance network to shape a delayed quasi-rectangular pulse. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:113-116 [Conf]
  30. Jofre Pallares, Justo Sabadell, Francesc Serra-Graells
    Modeling all-MOS log filters and its application to Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:117-120 [Conf]
  31. Sandro A. P. Haddad, Richard Houben, Wouter A. Serdijn
    Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:121-124 [Conf]
  32. Øivind Næss, Espen A. Olsen, Yngvar Berg, Tor Sverre Lande
    A low voltage second order biquad using pseudo floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:125-128 [Conf]
  33. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca
    Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:129-132 [Conf]
  34. Nuno F. Paulino, M. Serrazina, João Goes, Adolfo Steiger-Garção
    Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:133-136 [Conf]
  35. Cheuk-Yiu Ng, Mitchai Chongcheawchamnan, Ian D. Robertson, K. Cho
    Resistive FET IQ vector modulator using multilayer photoimageable thick-film technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:137-140 [Conf]
  36. Surachet Khucharoensin, Varakorn Kasemsuwan
    High-speed low input impedance CMOS current comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:141-144 [Conf]
  37. G. Evans, João Goes, Adolfo Steiger-Garção, Manuel Duarte Ortigueira, Nuno F. Paulino, Jilseph Lopes Silva
    Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:145-148 [Conf]
  38. Dusan M. Milosevic, Johan van der Tang, Arthur H. M. van Roermund
    On the feasibility of application of class E RF power amplifiers in UMTS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:149-152 [Conf]
  39. Gianluca Giustolisi, Gaetano Palumbo
    A novel 1-V class-AB transconductor for improving speed performance in SC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:153-156 [Conf]
  40. J. Martinez-Heredia, Antonio Jesús Torralba Silgado, Ramón González Carvajal, Jaime Ramírez-Angulo
    A new 1.5V linear transconductor with high output impedance in a large bandwidth. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:157-160 [Conf]
  41. Adrian Leuciuc
    A wide linear range low-voltage transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:161-164 [Conf]
  42. Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín
    Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:165-168 [Conf]
  43. Timothy G. Constandinou, Julius Georgiou, Chris Toumazou
    An auto-input-offset removing floating gate pseudo-differential transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:169-172 [Conf]
  44. S. Shang, Shahriar Mirabbasi, Resve A. Saleh
    A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:173-176 [Conf]
  45. Liwei Sheng, L. E. Larson
    A general theory of third-order intermodulation distortion in common-emitter radio frequency circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:177-180 [Conf]
  46. Antônio Carlos M. de Queiroz
    Capacitively coupled multiple resonance networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:181-184 [Conf]
  47. Kyoung-Hoi Koo, Jin-Ho Seo, Joe-Whui Kim
    Digitally tuneable on-chip resistor in CMOS for high-speed data transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:185-188 [Conf]
  48. Alfredo Arnaud, Carlos Galup-Montoro
    Simple noise formulas for MOS analog design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:189-192 [Conf]
  49. Esteban Tlelo-Cuautle, Alejandro Díaz-Sánchez
    An heuristic circuit-generation technique for the design-automation of analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:193-196 [Conf]
  50. Romero Tavares, B. Vaz, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção
    Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:197-200 [Conf]
  51. Alan A. Stocker
    Compact integrated transconductance amplifier circuit for temporal differentiation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:201-204 [Conf]
  52. S. Sridharan, Ghanshyam Nayak, P. R. Mukund
    LNA design optimization with reference to ESD protection circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:205-208 [Conf]
  53. Byunghoo Jung, Anand Gopinath, Ramesh Harjani
    A novel noise optimization design technique for radio frequency low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:209-212 [Conf]
  54. G. Girlando, Egidio Ragonese, Alessandro Italiano, Giovanni Palmisano
    Bipolar LNA design at different operating frequencies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:213-216 [Conf]
  55. Tommy Kwong-Kin Tsang, Mourad N. El-Gamal
    Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:217-220 [Conf]
  56. Jongrit Lerdworatawee, Won Namgoong
    Low noise amplifier design for ultra-wideband radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:221-224 [Conf]
  57. Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
    A 1-V CMOS output stage with high linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:225-228 [Conf]
  58. Chih-Wen Lu
    A new rail-to-rail driving scheme and a low-power high-speed output buffer amplifier for AMLCD column driver application. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:229-232 [Conf]
  59. Gianluca Giustolisi, Gaetano Palumbo
    A new method for evaluating harmonic distortion in push-pull output stages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:233-236 [Conf]
  60. Antonio Jesús Torralba Silgado, Ramón González Carvajal, Juan Antonio Gómez Galán, Jaime Ramírez-Angulo
    A new compact low-power high slew rate class AB CMOS buffer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:237-240 [Conf]
  61. J. S. Shor, Y. Polansky, Yaen Yaacov Sofer, E. Maayan
    Self-regulated four-phased charge pump with boosted wells. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:241-244 [Conf]
  62. Chih-Lung Hsiao, Ro-Min Weng, Kun-Yi Lin
    A 1V fully differential CMOS LNA for 2.4GHz application. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:245-248 [Conf]
  63. Ahmet Aksen, B. Siddik Yarman
    A parametric approach to describe distributed two-ports with lumped discontinuities for the design of broadband MMICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:249-252 [Conf]
  64. Hyeon-Min Bae, Naresh R. Shanbhag
    High bandwidth transimpedance amplifier design using active transmission lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:253-256 [Conf]
  65. Gang Xu, Jiren Yuan
    A Differential Difference Comparator for multi-step A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:257-260 [Conf]
  66. Enno Karel De Lange, Oscar De Feo, Arie van Staveren
    Modelling differential pairs for low-distortion amplifier design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:261-264 [Conf]
  67. HaiBin Huang, Ezz I. El-Masry
    A fast settling CMOS operational amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:265-268 [Conf]
  68. Antonio Jesús Torralba Silgado, Ramón González Carvajal, Fernando Muñoz Chavero, Jaime Ramírez-Angulo
    New output stage for low supply voltage, high-performance CMOS current mirrors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:269-272 [Conf]
  69. Saeid Mehrmanesh, Hesam Amir Aslanzadeh, M. B. Vahidfar, Seyed Mojtaba Atarodi
    A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:273-276 [Conf]
  70. Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín
    1-V quasi constant-g/sub m/ input/output rail-to-rail CMOS op-amp. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:277-280 [Conf]
  71. Sohrab Samadian, Ryoji Hayashi, Asad A. Abidi
    Low power demodulators with phase quantization for a zero-IF Bluetooth receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:281-284 [Conf]
  72. Sungho Beck, Myung-woon Hwang, Sang-Hoon Lee, Gyu-Hyeong Cho, Jong-Ryul Lee
    A precise temperature-insensitive and linear-in-dB variable gain amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:285-288 [Conf]
  73. F. Carrara, P. Filoramo, Giovanni Palmisano
    High-dynamic-range decibel-linear IF variable-gain amplifier with temperature compensation for WCDMA applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:289-292 [Conf]
  74. Ertan Zencir, Numan Sadi Dogan, Ercument Arvas, Mohammed Ketel
    A low-power low-noise amplifier in 0.35µm SOI CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:293-296 [Conf]
  75. Ming-Dou Ker, Chien-Ming Lee
    Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:297-300 [Conf]
  76. Eugenio Culurciello, Andreas G. Andreou
    An 8-bit, 1mW successive approximation ADC in SOI CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:301-304 [Conf]
  77. H. C. M. Santos, Ana Isabela Araújo Cunha
    Application of ACM model to the design of CMOS OTA through a graphical approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:305-308 [Conf]
  78. D. Weiler, T. J. J. van den Boom, Bedrich J. Hosticka
    Resolution prediction for bandpass-Sigma-Delta-modulators using SIMULINK behavior simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:309-312 [Conf]
  79. R. F. Salem, Maged S. Tawfik, H. F. Ragaie
    A symmetric quadrature-less image rejection architecture for RF receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:313-316 [Conf]
  80. Zheng Jihua, Li Yongming, Chen Hongyi
    A low-power low-noise 600MHz CMOS IF demodulator for superheterodyne receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:317-320 [Conf]
  81. Aleksandar Tasic, Wouter A. Serdijn, John R. Long
    Matching of low-noise amplifiers at high frequencies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:321-324 [Conf]
  82. Zhan Xu, Ezz I. El-Masry
    Design and optimization of CMOS class-E power amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:325-328 [Conf]
  83. Ming-Chang Sun, Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng
    A 2.4 GHz CMOS image-reject low noise amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:329-332 [Conf]
  84. Paolo Crippa, Simone Orcioni, F. Ricciardi, Claudio Turchetti
    Design of a 4.4 to 5 GHz LNA in 0.25µm SiGe BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:333-336 [Conf]
  85. Joon-Jea Sung, Guen-Soon Kang, Suki Kim
    A CMOS infrared optical signal processor for remote control. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:337-340 [Conf]
  86. Bendong Sun, Fei Yuan
    A new differential CMOS current pre-amplifier for optical communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:341-344 [Conf]
  87. Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin
    Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:345-348 [Conf]
  88. Khanittha Kaewdang, Chalermpan Fongsamut, Wanlop Surakampontorn
    A wide-band current-mode OTA-based analog multiplier-divider. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:349-352 [Conf]
  89. Chengming He, Degang Chen, Randall L. Geiger
    A low-voltage compatible two-stage amplifier with /spl ges/120 dB gain in standard digital CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:353-356 [Conf]
  90. Alessandro Savio, Anna Richelli, Luigi Colalongo, Zsolt Miklós Kovács-Vajna
    A fully-integrated self-tuned transformer based step-up converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:357-360 [Conf]
  91. U. Dasgupta, Yong Ping Xu
    Effects of resistive loading on unity gain frequency of two-stage CMOS operational amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:361-364 [Conf]
  92. Jozef Adut, José Silva-Martínez
    Cascode transconductance amplifiers for HF switched-capacitor applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:365-368 [Conf]
  93. Janusz Zarebski, Krzysztof Górecki
    The electrothermal model of the linear power supplies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:369-372 [Conf]
  94. Yamu Hu, Mohumud Sowan
    A 900 mV 25µW high PSRR CMOS voltage reference dedicated to implantable micro-devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:373-376 [Conf]
  95. A. Pretelli, Anna Richelli, Luigi Colalongo, Zsolt Miklós Kovács-Vajna
    Increasing the immunity to electromagnetic interferences in a bandgap voltage reference. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:377-380 [Conf]
  96. Saeid Mehrmanesh, M. B. Vahidfar, Hesam Amir Aslanzadeh, Seyed Mojtaba Atarodi
    A 1-volt, high PSRR, CMOS bandgap voltage reference. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:381-384 [Conf]
  97. Soliman A. Mahmoud, Inas A. Awad
    New CMOS balanced output transconductor and application to GM-C biquad filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:385-388 [Conf]
  98. Igor M. Filanovsky
    One class of transfer functions with monotonic step response. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:389-392 [Conf]
  99. Carlos Sánchez-López, Alejandro Díaz-Sánchez, Esteban Tlelo-Cuautle
    Analog implementation of MOS-translinear Morlet Wavelets. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:393-396 [Conf]
  100. Tsung-Sum Lee, Chi-Chang Lu
    A fully differential low-voltage CMOS high-speed track-and-hold circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:397-400 [Conf]
  101. Aleksandar Tasic, Wouter A. Serdijn, John R. Long
    Adaptivity figures of merit and K-rail diagrams - comprehensive performance characterization of low-noise amplifiers and voltage-controlled oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:401-404 [Conf]
  102. Boonchai Boonchu, Wanlop Surakampontorn
    A CMOS current-mode squarer/rectifier circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:405-408 [Conf]
  103. Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas, M. Gloanec, E. Leclerc, Bernard Lefebvre
    Broad-band transimpedance amplifier for multigigabit-per-second (40 Gbps) optical communication systems in 0.135µm PHEMT technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:409-412 [Conf]
  104. Nikos Naskas, Yannis Papananos
    A new non-iterative, adaptive baseband predistortion method for high power rf amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:413-416 [Conf]
  105. T. H. Huang, Ertan Zencir, M. R. Yuce, Numan Sadi Dogan, Wentai Liu, Ercument Arvas
    A 22-mW 435 MHz silicon on insulator CMOS high-gain LNA for subsampling receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:417-420 [Conf]
  106. Aleksandar Tasic, Wouter A. Serdijn, John R. Long
    Concept of transformer-feedback degeneration of low-noise amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:421-424 [Conf]
  107. Michele Quarantelli, Marco Poles, Marco Pasotti, Pier Luigi Rolandi
    A high compliance CMOS current source for low voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:425-428 [Conf]
  108. Christian Falconi, Arnaldo D'Amico, Marco Faccio
    Design of accurate analog circuits for low voltage low power CMOS systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:429-432 [Conf]
  109. K. Moolpho, Jitkasem Ngarmnil, S. Sitjongsataporn
    A high speed low input current low voltage CMOS current comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:433-436 [Conf]
  110. N. Srirattana, Muhammad S. Qureshi, A. Aude, V. Krishnamurthy, Deuk Hyoun Heo, Phillip E. Allen, Joy Laskar
    SiGe HBT power amplifier for IS-95 CDMA using a novel process, voltage, and temperature insensitive biasing scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:437-440 [Conf]
  111. Eric Kerherve, M. Hazouard, L. Courcelle, P. Jarry
    Large-signal S-parameters CAD technique applied to power amplifier design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:441-444 [Conf]
  112. C. Tongchoi, Mitchai Chongcheawchamnan, Apisak Worapishet
    Lumped element based Doherty power amplifier topology in CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:445-448 [Conf]
  113. Tang Tat Hung, Mourad N. El-Gamal
    Class-E CMOS power amplifiers for RF applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:449-452 [Conf]
  114. Yorgos Palaskas, Yannis P. Tsividis
    Power-area-DR-frequency-selectivity tradeoffs in weakly nonlinear active filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:453-456 [Conf]
  115. Jaeyoung Shin, Sunki Min, Soosun Kim, Joongho Choi, Soohyoung Lee, Hojin Park, Jaewhui Kim
    3.3-V baseband Gm-C filters for wireless transceiver applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:457-460 [Conf]
  116. Chun-Ming Chang, Bashir M. Al-Hashimi
    Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:461-464 [Conf]
  117. Shahram Minaei, Oguzhan Cicekoglu
    A new resistorless electronically tunable voltage-mode first-order phase equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:465-468 [Conf]
  118. Drazen Jurisic, George S. Moschytz, Neven Mijat
    Low-noise low-power allpole active-RC filters minimizing resistor level. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:469-472 [Conf]
  119. Deepa S. Parthasarathy, Ramesh Harjani
    Novel integratable notch filter implementation for 100 dB image rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:473-476 [Conf]
  120. Eduardo Rapoport, Fernando Antonio Pinto Baruqui, Antonio Petraglia
    Tunable analog loudspeaker crossover network. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:477-480 [Conf]
  121. Jen-Shiun Chiang, Hsueh-Ping Chen, Cheng-ming Ying
    A 1V 0.54µW fourth order switched capacitor filter with switched opamp technique for cardiac pacemaker sensing channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:481-484 [Conf]
  122. C. Frost, G. Levy, B. Allison
    A CMOS 2 MHz self-calibrating bandpass filter for personal area networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:485-488 [Conf]
  123. Ahmed Emira, Edgar Sánchez-Sinencio
    A low-power CMOS complex filter for Bluetooth with frequency tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:489-492 [Conf]
  124. Stefano D'Amico, Andrea Baschirotto
    0.18µ CMOS Gm-C digitally tuned filter for telecom receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:493-496 [Conf]
  125. P. Sirinamaratana, N. Wongkomet
    A 0.7µm CMOS anti-aliasing filter for non-oversampled video signal applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:497-500 [Conf]
  126. Armin Tajalli, Seyed Mojtaba Atarodi
    A compact biquadratic g/sub m/-C filter structure for low-voltage and high frequency applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:501-504 [Conf]
  127. Masayuki Kawamata
    On the invariance of the second-order modes of continuous-time systems under general frequency transformation [analog filters]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:505-508 [Conf]
  128. Roman Kaszynski
    Properties of analog systems with varying parameters [averaging/low-pass filters]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:509-512 [Conf]
  129. Behrouz Nowrouzian, Arthur T. G. Fuller
    A novel approach to the design and synthesis of general-order Bode-type variable-amplitude active-RC equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:513-516 [Conf]
  130. Luo Zhenying, Li Ming Fu, Yong Lian, S. C. Rustagi
    CMOS transconductor design for VHF filtering applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:517-520 [Conf]
  131. Armin Tajalli, Seyed Mojtaba Atarodi
    Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:521-524 [Conf]
  132. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:525-528 [Conf]
  133. P. Tangtisanon, A. Khempila, N. Panyanouvong, S. Saetia, K. Janchitrapongvej, S. Sudo, M. Teramoto
    The design of an active band pass filter using uniformly distributed RC line. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:529-532 [Conf]
  134. Brent Maundy, Ezz I. El-Masry, Peter B. Aronhime
    Novel high performance single amplifier biquads [voltage mode filters]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:533-536 [Conf]
  135. Kazuyuki Wada, Yoshiaki Tadokoro
    RC polyphase filter with flat gain characteristic. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:537-540 [Conf]
  136. Amorn Jiraseree-amornkun, Nobuo Fujii, Wanlop Surakampontorn
    Realization of electronically tunable ladder filters using multi-output current controlled conveyors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:541-544 [Conf]
  137. Mykhaylo A. Teplechuk, John I. Sewell
    Log-domain complex filter design with XFILTER. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:545-548 [Conf]
  138. H. J. Ko, Robert M. Fox
    Comparison of currents in differential log-domain filters with common-mode feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:549-552 [Conf]
  139. Jirayuth Mahattanakul, Sitthichai Pookaiyaudom
    Fully-differential log-domain integrator with orthogonal common-mode and differential-mode responses. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:553-556 [Conf]
  140. Belén Calvo, Maria Teresa Sanz, Santiago Celma, Pedro A. Martínez
    A CMOS digitally tunable transconductor for video frequency operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:557-560 [Conf]
  141. Saeid Mehrmanesh, M. B. Vahidfar, Hesam Amir Aslanzadeh, Seyed Mojtaba Atarodi
    An ultra low-voltage Gm-C filter for video applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:561-564 [Conf]
  142. Andrea Maniero, Andrea Gerosa, Andrea Neviani
    Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:565-568 [Conf]
  143. André van Schaik, Craig T. Jin
    The tau-cell: a new method for the implementation of arbitrary differential equations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:569-572 [Conf]
  144. Apinunt Thanachayanont, S. Sae-Ngow
    Inductorless RF amplifier with tuneable band-selection and image rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:573-576 [Conf]
  145. H. Ahmed, Chris DeVries, Ralph Mason
    RF, Q-enhanced bandpass filters in standard 0.18µm CMOS with direct digital tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:577-580 [Conf]
  146. Wiset Saksiri, Monai Krairiksh
    Lumped element model approach for the bandwidth enhancement of coupled microstrip antenna. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:581-584 [Conf]
  147. Vinita Vasudevan
    A time-domain technique for computation of noise spectral density in switched capacitor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:585-588 [Conf]
  148. Ramón González Carvajal, Juan Antonio Gómez Galán, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado
    New low-power low-voltage differential class-AB OTA for SC circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:589-592 [Conf]
  149. Gerry Quilligan, D. P. Burton
    A 0.35µm CMOS voltage derivative sensor with sign and inflection outputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:593-596 [Conf]
  150. José L. Ausín, Miguel Angel Domínguez, J. Francisco Duque-Carrillo, Guido Torelli
    Noise-shaping modulation in high-Q SC filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:597-600 [Conf]
  151. José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli, Jorge Sánchez Valverde
    Non-uniform sampling SC circuits based on noise-shaping feedback coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:601-604 [Conf]
  152. Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
    Design of low-voltage low-power SC filters for high-frequency applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:605-608 [Conf]
  153. Inchang Seo, Robert M. Fox
    Low-power switched-capacitor filters using charge transfer integrators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:609-612 [Conf]
  154. Shuenn-Yuh Lee, Yueh-Lun Tsai, Wei-Zen Su, Po-Hui Yang
    A 2.5 V switched-current sigma-delta modulator with a novel class AB memory cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:613-616 [Conf]
  155. Kasin Vichienchom, Wentai Liu
    Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:617-620 [Conf]
  156. Alistair McEwan, Steve Collins
    Analogue interpolation based direct digital frequency synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:621-624 [Conf]
  157. Charan Meenakarn, Apinunt Thanachayanont
    A sine-output ROM-less direct digital frequency synthesiser using a polynomial approximation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:625-628 [Conf]
  158. U. Yodprasit, Christian C. Enz
    Nonlinear analysis of a Colpitts injection-locked frequency divider. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:629-632 [Conf]
  159. Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng
    Low-power CMOS PLL for clock generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:633-636 [Conf]
  160. Marc Tiebout
    Physical scaling of integrated inductor layout and model and its application to WLAN VCO design at 11GHz and 17GHz. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:637-640 [Conf]
  161. Tser-Yu Lin, Ying-Zong Juang, Hung-Yu Wang, Chin-Fong Chiu
    A low power 2.2-2.6GHz CMOS VCO with a symmetrical spiral inductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:641-644 [Conf]
  162. Lixin Yang, Jiren Yuan
    An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:645-648 [Conf]
  163. Kee-Chee Tiew, J. Cusey, Randall L. Geiger
    Inflection point correction for voltage references. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:649-652 [Conf]
  164. Thilak Senanayake, Tamotsu Ninomiya
    High-current clamp for fast-response load transitions of DC-DC converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:653-656 [Conf]
  165. Rola A. Baki, Mourad N. El-Gamal
    A new CMOS charge pump for low-voltage (1V) high-speed PLL applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:657-660 [Conf]
  166. Xiaoyan Wang, Pietro Andreani
    Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:661-664 [Conf]
  167. Michael S. McCorquodale, Mei Kim Ding, Richard B. Brown
    Study and simulation of CMOS LC oscillator phase noise and jitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:665-668 [Conf]
  168. Jing-Hong Conan Zhan, Kyle Maurice, Jon S. Duster, Kevin T. Kornegay
    Analysis of emitter degenerated LC oscillators using bipolar technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:669-672 [Conf]
  169. Aleksandar Tasic, Wouter A. Serdijn, John R. Long
    Low-noise biasing of voltage-controlled oscillators by means of resonant inductive degeneration. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:673-676 [Conf]
  170. Juan Antonio Gómez Galán, Ramón González Carvajal, Fernando Muñoz Chavero, Antonio Jesús Torralba Silgado, Jaime Ramírez-Angulo
    A low-power low-voltage OTA-C sinusoidal oscillator with more than two decades of linear tuning range. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:677-680 [Conf]
  171. Wim Michielsen, Li-Rong Zheng, Hannu Tenhunen
    Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:681-684 [Conf]
  172. Tony Pialis, Khoman Phang
    Analysis of timing jitter in ring oscillators due to power supply noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:685-688 [Conf]
  173. Luís Bica Oliveira, Jorge R. Fernandes, Michiel H. L. Kouwenhoven, Chris van den Bos, Chris J. M. Verhoeven
    A quadrature relaxation oscillator-mixer in CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:689-692 [Conf]
  174. Krishnakumar Sundaresan, Keith C. Brouse, Kongpop U-Yen, Farrokh Ayazi, Phillip E. Allen
    A 7-MHz process, temperature and supply compensated clock oscillator in 0.25µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:693-696 [Conf]
  175. M. Jamal Deen, Mehdi H. Kazemeini, Susan Nuseh
    Performance characteristics of an ultra-low power VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:697-700 [Conf]
  176. Mehdi H. Kazemeini, M. Jamal Deen, Susan Nuseh
    Phase noise in a back-gate biased low-voltage VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:701-704 [Conf]
  177. Xibo Zhang, Philip K. T. Mok, Mansun Chan, Ping K. Ko
    Large-signal and phase noise performance analysis of active inductor tunable oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:705-708 [Conf]
  178. Robert Charles Koons, John R. Long
    An inductively-tuned quadrature oscillator with extended frequency control range. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:709-712 [Conf]
  179. Sawat Bunnjaweht, M. J. Underhill, Ian D. Robertson
    Sideband noise reduction in transposed gain oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:713-716 [Conf]
  180. Chao Su, Sreenath Thoka, Kee-Chee Tiew, Randall L. Geiger
    A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:717-720 [Conf]
  181. Syed Irfan Ahmed, Ralph D. Mason
    A dual edge-triggered phase-frequency detector architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:721-724 [Conf]
  182. Darius Jakonis, Christer Svensson
    A 1.6 GHz downconversion sampling mixer in CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:725-728 [Conf]
  183. Omid Oliaei
    Extraction of timing jitter from phase noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:729-732 [Conf]
  184. Joohwan Park, Franco Maloberti
    Phase noise improvement in fractional-N synthesizer with 90/spl deg/ phase shift lock. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:733-736 [Conf]
  185. Sami Karvonen, Thomas Riley, Juha Kostamovaara
    On the effects of timing jitter in charge sampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:737-740 [Conf]
  186. Haigang Feng, Rouying Zhan, Guang Chen, Qiong Wu, Xiaokang Guan, Haolu Xie, Albert Z. Wang
    Bonding-pad-oriented on-chip ESD protection structures for ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:741-744 [Conf]
  187. Gang Xu, Jiren Yuan
    Performance analysis of general charge sampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:745-748 [Conf]
  188. Xiaofeng Lin, Guangbin Zhang, Jin Liu
    Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:749-752 [Conf]
  189. Ken Yamamoto, Minoru Fujishima, Koichiro Hoh
    Optimization of shield structures in analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:753-756 [Conf]
  190. Young-Mi Lee, Ju-Sang Lee, Sang Jin Lee, Ri-A Ju
    Design of a frequency synthesizer for WCDMA in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:757-760 [Conf]
  191. Li Yang, J. S. Yuan
    Design of enhancement current-balanced logic for mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:761-764 [Conf]
  192. Phaophak Sirisuk, Apisak Worapishet, Saifon Tanoi
    An efficient mixed-signal architecture for minimum output energy blind multiuser detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:765-768 [Conf]
  193. Roman Genov, Gert Cauwenberghs
    Algorithmic partial analog-to-digital conversion in mixed-signal array processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:769-772 [Conf]
  194. Eric E. Fabris, Luigi Carro, Sergio Bampi
    An analog signal interface with constant performance for SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:773-776 [Conf]
  195. Milutin Stanacevic, Gert Cauwenberghs
    Mixed-signal gradient flow bearing estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:777-780 [Conf]
  196. Jaime Ramírez-Angulo, Carlos Urquidi, Ramón González Carvajal, Antonio Jesús Torralba Silgado
    Sub-volt supply analog circuits based on quasi-floating gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:781-784 [Conf]
  197. Jouko Vankka, Jaakko Lindeberg, Kari Halonen
    Direct digital synthesizer with tunable phase and amplitude error feedback structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:785-788 [Conf]
  198. S. C. Rustagi, Chun-Geik Tan
    Equivalent circuit models for stacked spiral inductors in deep submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:789-792 [Conf]
  199. Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy
    A CMOS current-controlled oscillator and its applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:793-796 [Conf]
  200. Hyung Ki Ahn, In-Cheol Park, Beomsup Kim
    A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:797-800 [Conf]
  201. Antonio J. López-Martín, Jaime Ramírez-Angulo, Ramón González Carvajal
    Low-voltage low-power wideband CMOS current conveyors based on the flipped voltage follower. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:801-804 [Conf]
  202. Jaime Ramírez-Angulo, Ramón González Carvajal, Gladys Omayra Ducoudray
    New very compact CMOS continuous-time low-voltage analog rank-order filter architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:805-808 [Conf]
  203. Yu-Chuan Shih, Chung-Yu Wu
    An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:809-812 [Conf]
  204. Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, C. Lackey
    Low-voltage closed-loop amplifier circuits based on quasi-floating gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:813-816 [Conf]
  205. Fernando Muñoz Chavero, Antonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado, Meghraj Kachare, Bernardo Palomo Vázquez
    Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:817-820 [Conf]
  206. Tsung-Sum Lee, Li-Dyi Luo, Chin-Sheng Lin
    Design techniques for a fully differential low voltage low-power flash analog to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:821-824 [Conf]
  207. Väinö Hakkarainen, Lauri Sumanen, Mikko Aho, Mikko Waltari, Kari Halonen
    A self-calibration technique for time-interleaved pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:825-828 [Conf]
  208. Jipeng Li, Un-Ku Moon
    An extended radix-based digital calibration technique for multi-stage ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:829-832 [Conf]
  209. Kamal El-Sankary, Ali Assi, Mohamad Sawan
    New sampling method to improve the SFDR of time-interleaved ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:833-836 [Conf]
  210. Miquel Albiol, José Luis González, Eduard Alarcón
    Improved current-source sizing for high-speed high-accuracy current steering D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:837-840 [Conf]
  211. Zeynep Toprak Deniz, Yusuf Leblebici
    Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:841-844 [Conf]
  212. Liviu Chiaburu, Svante Signell
    A method to reduce power consumption in pipelined A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:845-848 [Conf]
  213. Pedro M. Figueiredo, João C. Vital
    Analysis of the averaging technique in flash ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:849-852 [Conf]
  214. D. R. Beck, David J. Allstot, D. Garrity
    An 8-bit, 1.8 V, 20 MSample/s analog-to-digital converter using low gain opamps. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:853-856 [Conf]
  215. G. Ding, Catherine Dehollain, Michel J. Declercq, Kamran Azadet
    Frequency-interleaving technique for high-speed A/D conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:857-860 [Conf]
  216. S. Luschas, H.-S. Lee
    Output impedance requirements for DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:861-864 [Conf]
  217. Liviu Chiaburu, Svante Signell
    An improved binary algorithmic A/D converter architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:865-868 [Conf]
  218. Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, Seung-Hoon Lee
    A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:869-872 [Conf]
  219. Waisiu Law, Jianjun Guo, Charles T. Peach, Ward J. Helms, David J. Allstot
    A monotonic digital calibration technique for pipelined data converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:873-876 [Conf]
  220. M. Unterweissacher, João Goes, Nuno F. Paulino, G. Evans, Manuel Duarte Ortigueira
    Efficient digital self-calibration of video-rate pipeline ADCs using white Gaussian noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:877-880 [Conf]
  221. Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
    A digital background calibration technique for pipelined analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:881-884 [Conf]
  222. Hesam Amir Aslanzadeh, Saeid Mehrmanesh, M. B. Vahidfar, Seyed Mojtaba Atarodi
    A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:885-888 [Conf]
  223. Jianjun Guo, Waisiu Law, Charles T. Peach, Ward J. Helms, David J. Allstot
    A mixed-signal calibration technique for low-voltage CMOS 1.5-bit/stage pipeline data converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:889-892 [Conf]
  224. F. Vessal, C. Andre T. Salama
    An 8-bit 2-GSample/s analog-to-digital converter in 0.5µm SiGe technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:893-896 [Conf]
  225. Kamran Farzan, David A. Johns
    A power-efficient architecture for high-speed D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:897-900 [Conf]
  226. Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang
    1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:901-904 [Conf]
  227. C. Sim, Chris Toumazou
    Power efficient scalable precision rational digital to analogue converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:905-908 [Conf]
  228. Zhongjun Yu, Degang Chen, Randall L. Geiger
    1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:909-912 [Conf]
  229. C. Rebai, Dominique Dallet, Philippe Marchegay
    High order 1-bit digital sigma delta modulation for on chip analogue signal sources. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:913-916 [Conf]
  230. Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Direct digital synthesizer with tunable delta sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:917-920 [Conf]
  231. Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
    A 1 V, 12-bit wideband continuous-time /spl Sigma//spl Delta/ modulator for UMTS applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:921-924 [Conf]
  232. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
    Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:925-928 [Conf]
  233. Denis Daly, Anthony Chan Carusone
    A sigma-delta based open-loop frequency modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:929-932 [Conf]
  234. Lei Wang, Sherif H. K. Embabi
    Low voltage 2-path SC bandpass /spl Delta//spl Sigma/ modulator without bootstrapper. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:933-936 [Conf]
  235. Zhenghong Wang, Xieting Ling, Bo Hu
    A low-complexity low-distortion topology for wideband delta-sigma ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:937-940 [Conf]
  236. Minho Kwon, Jungyoon Lee, Gunhee Han
    A time-interleaved switched-capacitor band-pass delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:941-944 [Conf]
  237. Mitsuhiko Yagyu
    Design of noise shaping FIR filters by minimizing in-band peak amplitude for stable single- and multi-bit data converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:945-948 [Conf]
  238. R. T. Silva, Jorge R. Fernandes
    A low-power CMOS folding and interpolation A/D converter with error correction. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:949-952 [Conf]
  239. Vincenzo Ferragina, Andrea Fornasari, Umberto Gatti, Piero Malcovati, Franco Maloberti
    Gain and offset mismatch calibration in multi-path sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:953-956 [Conf]
  240. Omid Oliaei
    Continuous-time sigma-delta modulator incorporating semi-digital FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:957-960 [Conf]
  241. Jianxin Zhang, Paul V. Brennan, Dai Jiang, E. Vinogradova, P. D. Smith
    Stability analysis of a sigma delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:961-964 [Conf]
  242. Janusz A. Starzyk, Russell P. Mohn
    Cost-oriented design of a 14-bit current steering DAC macrocell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:965-968 [Conf]
  243. Marko Kosunen, Jouko Vankka, F. Teikari, Kari Halonen
    DNL and INL yield models for a current-steering D/A converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:969-972 [Conf]
  244. Tao Chen, Georges G. E. Gielen
    Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:973-976 [Conf]
  245. Konstantinos Doris, Arthur H. M. van Roermund, Domine Leenaerts
    Mismatch-based timing errors in current steering DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:977-980 [Conf]
  246. Huseyin Dine, Franco Maloberti
    An 8-bit current mode ripple folding A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:981-984 [Conf]
  247. Peter Kiss, Jesus Arias, Dandan Li
    Stable high-order delta-sigma DACS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:985-988 [Conf]
  248. Luis Hernández, Susanna Patón
    Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:989-992 [Conf]
  249. Yu-Hong Lin, Da-Huei Lee, Cheng-Chung Yang, Tai-Haur Kuo
    High-speed DACs with random multiple data-weighted averaging algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:993-996 [Conf]
  250. Jen-Shiun Chiang, Pao-Chu Chou, Teng-Hung Chang
    Dual-mode sigma-delta modulator for wideband receiver applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:997-1000 [Conf]
  251. R. LeReverend, Izzet Kale, D. Guy, D. Morling, S. Morris
    An ultra-low power double-sampled A/D MASH /spl Sigma//spl Delta/ modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1001-1004 [Conf]
  252. Dag T. Wisland, Mats Erling Høvin, Tor Sverre Lande
    Quantization noise in the first-order non-feedback delta-sigma modulator with DC-input. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1005-1008 [Conf]
  253. Daeik D. Kim, Martin A. Brooke
    A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1009-1012 [Conf]
  254. Anurog Pulincherry, Mike Hufford, Eric Naviasky, Un-Ku Moon
    Continuous-time, frequency translating, bandpass delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1013-1016 [Conf]
  255. Teemu Salo, Saska Lindfors, Kari Halonen
    BP decimation filter for IF-sampling merged with BP /spl Sigma//spl Delta/-modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1017-1020 [Conf]
  256. Jörg Sauerbrey, M. Wittig, Doris Schmitt-Landsiedel, Roland Thewes
    0.65V sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1021-1024 [Conf]
  257. Jae Hoon Shim, In-Cheol Park, Beomsup Kim
    A hybrid delta-sigma modulator with adaptive calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1025-1028 [Conf]
  258. Frank Henkel, Ulrich Langmann
    Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1029-1032 [Conf]
  259. Amin Quasem Safarian, F. Sahandi, Seyed Mojtaba Atarodi
    A new low-power sigma-delta modulator with the reduced number of op-amps for speech band applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1033-1036 [Conf]
  260. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
    Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1037-1040 [Conf]
  261. X. Wang, Y. P. Xu, Z. Wang, S. Liw, W. H. Sun, L. S. Tan
    A bandpass sigma-delta modulator employing micro-mechanical resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1041-1044 [Conf]
  262. Mohammad Yavari, Omid Shoaei, Ali Afzali-Kusha
    A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1045-1048 [Conf]
  263. F. Esahani, Philipp Basedau, R. Ryter, R. Becker
    An 82 dB CMOS continuous-time complex bandpass sigma-delta ADC for GSM/EDGE. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1049-1052 [Conf]
  264. Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado
    New dual-quantization multibit sigma-delta modulators with digital noise-shaping. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1053-1056 [Conf]
  265. Lukas Dorrer, Antonio Di Giandomenico, Andreas Wiesbauer
    A 10-bit, 4 mW continuous-time sigma-delta ADC for UMTS in a 0.12µm CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1057-1060 [Conf]
  266. Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins
    A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1061-1064 [Conf]
  267. Marco Cassia, Peter Shah, Erik Bruun
    A spur-free fractional-N /spl Sigma//spl Delta/ PLL for GSM applications: linear model and simulations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1065-1068 [Conf]
  268. Jannik Hammel Nielsen, Erik Bruun
    A design methodology for power-efficient continuous-time Sigma-Delta A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1069-1072 [Conf]
  269. Yamu Hu, Zhijun Lu, Mohamad Sawan
    A low-voltage 38µW sigma-delta modulator dedicated to wireless signal recording applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1073-1076 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
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