Conferences in DBLP
Jai-Cheol Lee , Yu Hen Hu EDLICS: A New Relaxation-Based Electrical Circuit Simulation Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Senoo , Hiroaki Makino , Hideki Asai Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Masakatsu Nishigaki , Nobuyuki Tanaka , Hideki Asai Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. [Citation Graph (0, 0)][DBLP ] Conf ] Abdolreza Nabavi-Lishi , Nicholas C. Rumin Inverter-based Models for Current Analysis of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Zamlynski , Jan Ogrodzki Electro-Thermal Analysis of IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Shyh-Jye Jou , Mei-Fang Perng , Chauchin Su , C. K. Wang Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco V. Fernández , Piet Wambacq , Georges G. E. Gielen , Ángel Rodríguez-Vázquez , Willy M. C. Sansen Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Scott E. Greenfield , Marwan M. Hassoun Direct Hierarchical Symbolic Transient Analysis of Linear Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wlodzimierz M. Zuberek , A. Konczykowska , D. Martin An Approach to Integrated Numerical & Symbolic Circuit Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] C. C. Jong , Y. Y. H. Lam , S. S. Lim , T. S. Teng Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] N. A. Ramakrishna , Magdy A. Bayoumi Storage Allocation Strategies for Data Path Synthesis of ACICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Ren-Der Chen , Shiann-Rong Kuang Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kwangsoo Seo , Jeongyop Lee , Moonkey Lee Allocation of Multiport Memories in ASIC Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce A. Johnston , Peter J. W. Graumann , Laurence E. Turner DSP System Synthesis Including Variable Data Path Width. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Hu , Bradley S. Carlson A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Dutta , Sudip Nag , Kaushik Roy ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Bozena Kaminska High Level Synthesis with Testability Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Shujian Zhang , R. Byrne , Jon C. Muzio , D. Michael Miller Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Akachai Sang-In , Peter Y. K. Cheung A Method of Representative Fault Selection in Digital Circuits for ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Beom-Ik Cheon , Walter Anheier , Rainer Laur A New Strategy for Test Pattern Generation in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Franco Fummi , Donatella Sciuto Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Shung-Chih Chen , Ren-Der Chen A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Hirech , O. Florent , Alain Greiner , E. Rejouan A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Mineo Kaneko , Kazuhiro Sakaguchi Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Ziólko Optimal Placement of Heat Dissipating Elements. [Citation Graph (0, 0)][DBLP ] Conf ] H. Mauritz , Wolfgang Mathis Integration System as Adaptive Control System. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan , Pei-Yung Hsiao Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Paul Krivacek , Mark Harward Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph L. Ganley , James P. Cohoon Routing a Multi-Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles. [Citation Graph (0, 0)][DBLP ] Conf ] Dilvan de Abreu Moreira , Les T. Walczowski Automated Placement for a Leaf Cell Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Qu , M. A. Styblinski Statistical Characterization and Modeling of Analog Functional Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Qin Lu , Kimihiro Ogawa , Takehiko Adachi , Andrzej J. Strojwas Stochastic Interpolation Model Scheme for Statistical Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. Bandler , S. H. Chen , R. M. Biernacki , Kim Halskov Madsen The Huber Concept in Device Modeling, Circuit Diagnosis and Design Centering. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Su , Christopher Michael , Mohammed Ismail Statistical Constrained Optimization of Analog CMOS Circuits using Empirical Performance Models. [Citation Graph (0, 0)][DBLP ] Conf ] Leszek J. Opalski , Jacek Wojciechowski Application of the Piecewise Ellipsoidal Approximation Technique to Design Centering. [Citation Graph (0, 0)][DBLP ] Conf ] Morie E. Malowany , Gordon W. Roberts , Vinod K. Agarwal VAMP: A Hierarchical Framework for Design for Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. Bandler , R. M. Biernacki , S. H. Chen , P. A. Grobelny A CAD Environment for Performance and Yield Driven Circuit Design Employing Electromagnetic Field Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Syed A. Aftab , M. A. Styblinski IC Variability Minimization using a New Cp and Cpk Based Variability/Performance Measure. [Citation Graph (0, 0)][DBLP ] Conf ] J. C. Zhang Worst Case Design of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelhakim Safir , Baher Haroun , Krishnaiyan Thulasiraman A Floorplanner driven by Structural & Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Hsi Chen , Ioannis G. Tollis A New Approach to Floorplan Area Optimization: To Slice or not to Slice? [Citation Graph (0, 0)][DBLP ] Conf ] Tetsushi Koide , Yoshinori Katsura , Katsumi Yamatani , Shin'ichi Wakabayashi , Noriyoshi Yoshida A Floorplanning Method with Topological Constraint Manipulation. [Citation Graph (0, 0)][DBLP ] Conf ] P. Chin , Anthony Vannelli Interior Point Methods for Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Achim G. Hoffmann The Dynamic Locking Heuristic - A New Graph Partitioning Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten F. Ball , Peter V. Kraus , Dieter A. Mlynski Fuzzy Partitioning applied to VLSI-Floorplanning and Placement. [Citation Graph (0, 0)][DBLP ] Conf ] M. Kemal Unaltuna , Vijay Pitchumani A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiko Toyonaga , Shih-Tsung Yang , Toshiro Akino , Isao Shirakawa A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Yhonkyong Choi , Juhyun Lee , Chong S. Rim Automatic Functional Cell Generation in the Sea-of-Gates Layout Style. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Takeomi Tamesada , Akio Sakamoto A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Chip-Hong Chang Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw Deniziak , Krzysztof Sapiecha Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe F. Baake , Sorin A. Huss Scheduling of Signal Transition Graphs under Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jazi Eko Istiyanto , Sean Monaghan FPGA-Memory Tradeoff in the High-Level Synthesis of FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjive Agarwala , Patrick W. Bosshart A Linear Time Algorithm for Timing Directed Circuit Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Rousse , Alison J. Carter Exploring Delay/Area Trade-Offs of an LDI Filter Using a Natural Based Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Kunihiro Fujiyoshi , Yoji Kajitani , Hiroshi Niitsu Design of Optimum Totally Perfect Connection-Blocks of FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Shin'ichi Wakabayashi , Kazunori Isomoto , Tetsushi Koide , Noriyoshi Yoshida A Systolic Graph Partitioning Algorithm for VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dossis , James M. Noras , Gary J. Porter Synthesis of Customized Hardware from ADA. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. M. Heijiligers , H. A. Hilderink , Adwin H. Timmer , Jochen A. G. Jess NEAT: An Object Oriented High-Level Synthesis Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Song , Malgorzata Chrzanowska-Jeske Output Column Folding for Cellular-Architecture FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Caruso An Improved Algorithm for Boolean Factoring. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Khordoc , Eduard Cerny Modeling Cell Processing Hardware with Action Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Minjoong Rim , Rajiv Jain Estimating Performance Characteristics of Loop Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] William Y. M. Lai , C. K. Tse , C. H. Szeto Computer Formulation of Averaged Models for Periodically-Switched Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jukka Lahti Graphical Specification Methods for Digital Telecommuniation ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Tolga Çiloglu , Zafer Ünver A Novel Method for Discrete Coefficient FIR Digital Filter Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jouni Isoaho , Jari Nurmi An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] John Harris , Mark Chadwick , Tom Quan , Norbert Diesing , Edward MacRobbie Mixed Analog-Digital Simulation: The tools are here... is anyone really using them? [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Jerry Chih-Yuan Yang , Edmund M. Clarke , Xudong Zhao , Patrick C. McGeer Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Loïc Vandeventer , Jean François Santucci Using Binary Decision Diagrams to Speed up the Test Pattern Generation of Behavioral Circuit Descriptions Written in Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Fang Chao , Edwin Hsing-Mean Sha Retiming and Clock Skew for Synchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Chung Tsai , Malgorzata Marek-Sadowska Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. [Citation Graph (0, 0)][DBLP ] Conf ] Jérôme Fron , Jerry Chih-Yuan Yang , Maurizio Damiani , Giovanni De Micheli A Synthesis Framework Based on Trace and Automata Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Hu , Bradley S. Carlson Improved Lower Bounds for the Scheduling Optimization Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Stefano Quer Detecting hard faults with combined approximate forward/backward symbolic techniques. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva , Karem A. Sakallah Efficient and Robust Test Generation-Based Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Tae Jung , Chu Shik Jhon Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C.-H. Chang , Bing J. Sheu An Analog MOS Model for Circuit Simulation and Benchmark Test Results. [Citation Graph (0, 0)][DBLP ] Conf ] M. E. Kole , J. Smith , O. E. Herrmann Modeling Symmetry in Analog Electronic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dongfeng Zhao , Ray R. Chen GODPE: Global Optimization in Small Signal Device Model Parameter Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Jack Lau , Ping K. Ko , Philip C. Chan On the Modelling of a CMOS Magnetic Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Lallement , R. Bouchakour , T. Maurel A VDMOS transistor model taking into account the thermoelectrical interactions. [Citation Graph (0, 0)][DBLP ] Conf ] David I. Long , Sa'ad Medhat Behavioural Modelling of Mixed Signal ASICs: A new multi-level approach. [Citation Graph (0, 0)][DBLP ] Conf ] Ayman I. Kayssi , Karem A. Sakallah Macromodel Simplification Using Dimensional Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Moenclaey , Andreas Kaiser Accurate Modelling of the Non-Linear Settling Behaviour of Current Memory Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Georg Brachtendorf , Rainer Laur Modeling of Frequency-dependent Hysteresis with SPICE. [Citation Graph (0, 0)][DBLP ] Conf ] Zhihua Wang , Georges G. E. Gielen , Willy M. C. Sansen A Novel Method for the Fault Detection of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Salman Ahmed , Peter Y. K. Cheung Analog Fault Diagnosis - A Practical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Margherita Pillan , Donatella Sciuto Constraint Generation & Placement for Automatic Layout Design of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] K. K. Wee , R. J. Mack Towards Expandable and Generalised Analogue Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald S. Gyurcsik , George Gad-El-Karim , Griff L. Bilbro Sensitivity-Driven Placement of Analog Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Chávez Orzáez , Antonio Jesús Torralba Silgado , Leopoldo García Franquelo A Fuzzy-logic based Tool for Topology Selection in Analog Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] N. C. Horta , José E. Franca A Methodology for Automatic Generation of Data Conversion Topologies from Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Angel Aguirre Echánove , Jorge Chávez Orzáez , Antonio Jesús Torralba Silgado , Leopoldo García Franquelo Analog Design optimization by means of a Tabu Search Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mustafa Celik , O. Ocali , Mehmet Ali Tan , Abdullah Atalar Improving AWE Accuracy Using Multipoint Padé Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Ogrodzki , Dariusz Bukat Compact Modelling in Circuit Simulation: the General Purpose Analyser OPTIMA-3. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Peter Amann , Philippe Moeschler , Fausto Pellandini , Alain Vachoux , Charles Munk , Daniel Mlynek High-Level Specification of Behavioural Hardware Models with MODES. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Miura-Mattausch , Alexander Rahm , Michael Bollu , Ute Feldmann , Dominique Savignac A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation Time. [Citation Graph (0, 0)][DBLP ] Conf ] Hannu Jokinen , Martti Valtonen Small-Signal Analysis of Nonideal Switched-Capacitor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Stoy , Zebo Peng An Integrated Modelling Technique for Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Van Halen A Physical Charge-Based Model for the Space Charge Region of Abrupt and Linear Semiconductor Junctions. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul B. Deokar , Sachin S. Sapatnekar A Graph-Theoretic Approach to Clock Skew Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Ishida , Koichi Hayashi , Masakatsu Nishigaki , Hideki Asai Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bengt-Arne Molin , Sven Mattisson Concurrent Switch-Level Timing Simulation Based on Waveform Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Vijaya Gopal Bandi , Hideki Asai Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Ying-Wen Bai Interval Finite-Difference Methods for Digital MOS Circuits Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Keng-Hua Shi , A. K. Jastrzebski , Les T. Walczowski , J. Barnaby A Multi-Mode Simulation System for GaAs Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kewei Yang , Richard C. Meitzler , Andreas G. Andreou A Model for MOS Effective Channel Mobility with Emphasis in the Subthreshold and Transition Region. [Citation Graph (0, 0)][DBLP ] Conf ] Harish Kriplani , Farid N. Najm , Ibrahim N. Hajj Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luís Felipe Uebel , Sergio Bampi A Timing Model for VLSI CMOS Circuits Verification and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] A. B. van der Wal , Robert G. J. Arendsen , Aarnout Brombacher , O. E. Herrmann Hierarchical Statistical Verification of Large Full Custom CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Dong Chiang , Chia-Chi Chu A Systematic Search Method for Obtaining Multiple Local Optimal Solutions of Nonlinear Programming Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco V. Fernández , Georges G. E. Gielen , Lawrence Huelsman , Agnieszka Konczykowska , Stefano Manetti , Willy M. C. Sansen , Jiri Vlach Pleasures, Perils and Pitfalls of Symbolic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Qi-Jun Zhang , Michel S. Nakhla Signal Integrity Analysis and Optimization of VLSI Interconnects using Neural Network Models. [Citation Graph (0, 0)][DBLP ] Conf ] Todd D. Hodes , Bernard A. McCoy , Gabriel Robins Dynamically-Wiresized Elmore-Based Routing Constructions. [Citation Graph (0, 0)][DBLP ] Conf ] Wasim Khan , Sreekrishna Madhwapathy , Naveed A. Sherwani A Hierarchical Approach to Clock Routing in High Performance Systems. [Citation Graph (0, 0)][DBLP ] Conf ] T. W. Her , D. F. Wong Over-the-Cell Routing with Cell Orientations Consideration. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh Kumar Seghal , C. Y. Roger Chen , John M. Acken A High Performance General Purpose Multi-Point Signal Router. [Citation Graph (0, 0)][DBLP ] Conf ] Ira Pramanick , Hyder Ali Analysis and Experiments for a Parallel Solution to the All Pairs Shortest Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Masao Sato , Tatsuo Ohtsuki A Simultaneous Placement and Global Routing Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Henning Spruth , Frank M. Johannes , Kurt Antreich PHIroute: A Parallel Hierarchical Sea-of-Gates Router. [Citation Graph (0, 0)][DBLP ] Conf ] Juan A. Prieto , José M. Quintana , Adoración Rueda , José L. Huertas An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 