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IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2003 (conf/iscas/2003-5)

  1. Michael W. Baker, Serhii M. Zhak, Rahul Sarpeshkar
    A micropower envelope detector for audio applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:1-4 [Conf]
  2. Rizwan Bashirullah, Wentai Liu, Ying Ji, Gurhan Alper Kendir, Mohanasankar Sivaprakasam, Guoxing Wang, B. Pundi
    A smart bi-directional telemetry unit for retinal prosthetic device. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:5-8 [Conf]
  3. Alexander Frey, Martin Jenkner, Meinrad Schienle, Christian Paulus, Birgit Holzapfl, Petra Schindler-Bauer, Franz Hofmann, D. Kuhlmeier, J. Krause, J. Albers, W. Gumbrecht, Doris Schmitt-Landsiedel, Roland Thewes
    Design of an integrated potentiostat circuit for CMOS bio sensor chips. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:9-12 [Conf]
  4. G. Mulliken, Mihir Naware, A. Bandyopadhyay, Gert Cauwenberghs, Nitish Thakor
    Distributed neurochemical sensing: in vitro experiments. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:13-16 [Conf]
  5. Marek R. Ogiela, Ryszard Tadeusiewicz
    Visual signal processing and image understanding in biomedical systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:17-20 [Conf]
  6. Thitiporn Chanwimaluang, Guoliang Fan
    An efficient blood vessel detection algorithm for retinal images using local entropy thresholding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:21-24 [Conf]
  7. P. D. Cristea
    Phase analysis of DNA genomic signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:25-28 [Conf]
  8. Hamid Hassanpour, Mostefa Mesbah, Boualem Boashash
    Enhanced time-frequency features for neonatal EEG seizure detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:29-32 [Conf]
  9. Pega Zarjam, Mostefa Mesbah, Boualem Boashash
    An optimal feature set for seizure detection systems for newborn EEG signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:33-36 [Conf]
  10. Sandro A. P. Haddad, Sebastian Gieltjes, Richard Houben, Wouter A. Serdijn
    An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:37-40 [Conf]
  11. Timothy Kuan-Ta Lu, Michael W. Baker, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar
    A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:41-44 [Conf]
  12. Maysam Ghovanloo, Khalil Najafi
    A high-rate frequency shift keying demodulator chip for wireless biomedical implants. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:45-48 [Conf]
  13. Andrea Gerosa, Andrea Neviani
    A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:49-52 [Conf]
  14. Jonathan Coulombe, Jean-François Gervais, Mohamad Sawan
    A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:53-56 [Conf]
  15. Shuenn-Yuh Lee, Shyh-Chyang Lee, Jia-Jin Jason Chen
    VLSI implementation of wireless bi-directional communication circuits for micro-stimulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:57-60 [Conf]
  16. O. Omeni, Chris Toumazou
    A CMOS micro-power wideband data/power transfer system for biomedical implants. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:61-64 [Conf]
  17. Karn Opasjumruskit, Naiyavudhi Wongkomet
    A CMOS current-to-LCD interface for portable amperometric sensing systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:65-68 [Conf]
  18. Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi
    xLIW - a scaleable long instruction word. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:69-72 [Conf]
  19. H. S. Ng, Sui-Tung Mak, Kai-Pui Lam
    Field programmable gate arrays and analog implementation of BRIN for optimization problems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:73-76 [Conf]
  20. Kamran Farzan, David A. Johns
    A low-complexity power-efficient signaling scheme for chip-to-chip communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:77-80 [Conf]
  21. Robert Siegmund, Dietmar Müller
    Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:81-84 [Conf]
  22. Marcus van Ierssel, Tooraj Esmailian, Ali Sheikholeslami, P. S. Pasupathy
    Signaling capacity of FR4 PCB traces for chip-to-chip communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:85-88 [Conf]
  23. Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei
    A CMOS charge pump for sub-2.0 V operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:89-92 [Conf]
  24. Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun
    New dynamic logic-level converters for high performance application. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:93-96 [Conf]
  25. Ming-Dou Ker, Chia-Sheng Tsai
    Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:97-100 [Conf]
  26. Sang-Chul Moon, In-Cheol Park
    Area-efficient memory-based architecture for FFT processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:101-104 [Conf]
  27. Hoseok Chang, Wonchul Lee, Wonyong Sung
    Optimization of power consumption for an ARM7-based multimedia handheld device. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:105-108 [Conf]
  28. Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
    Loop scheduling for minimizing schedule length and switching activities. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:109-112 [Conf]
  29. Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
    Variable delay ripple carry adder with carry chain interrupt detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:113-116 [Conf]
  30. Jos Sulistyo, Dong Sam Ha
    5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:117-120 [Conf]
  31. Hwang-Cherng Chow, I-Chyn Wey
    A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:121-124 [Conf]
  32. Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan
    Low cost logarithmic techniques for high-precision computations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:125-128 [Conf]
  33. Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis
    A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:129-132 [Conf]
  34. Andrea Lodi, Carlo Chiesa, Fabio Campi, Mario Toma
    A flexible LUT-based carry chain for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:133-136 [Conf]
  35. K. J. Cho, E. M. Choi, J. G. Chung, M. S. Lim, J. W. Kim
    Low-error fixed-width squarer design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:137-140 [Conf]
  36. Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait
    Area-time optimal adder with relative placement generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:141-144 [Conf]
  37. Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria
    About the performances of the Advanced Encryption Standard in embedded systems with cache memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:145-148 [Conf]
  38. Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Thewhan KimU
    An efficient inverse multiplier/divider architecture for cryptography systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:149-152 [Conf]
  39. Nicolas Sklavos, Odysseas G. Koufopavlou
    On the hardware implementations of the SHA-2 (256, 384, 512) hash functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:153-156 [Conf]
  40. Wonjong Kim, Seungchul Kim, HanJin Cho, Kwang-youb Lee
    A fast-serial finite field multiplier without increasing the number of registers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:157-160 [Conf]
  41. K.-C. B. Tan, T. Arslan
    Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:161-164 [Conf]
  42. Harri Lampinen, Pauli Perälä, Olli Vainio
    Design of a self-timed asynchronous parallel FIR filter using CSCD. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:165-168 [Conf]
  43. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
    Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:169-172 [Conf]
  44. Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
    Area-effective FIR filter design for multiplier-less implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:173-176 [Conf]
  45. I. M. Hyjazie, Chunyan Wang
    An approach for improving the speed of content addressable memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:177-180 [Conf]
  46. Yu-Cheng Fan, Hen-Wai Tsao
    Watermarking based IP core protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:181-184 [Conf]
  47. Seong-Il Park, In-Cheol Park
    History-based memory mode prediction for improving memory performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:185-188 [Conf]
  48. Mutlu Avci, Tülay Yildirim
    A coding method for 123 decision diagram pass transistor logic circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:189-192 [Conf]
  49. Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin
    Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:193-196 [Conf]
  50. Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker
    An efficient transistor optimizer for custom circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:197-200 [Conf]
  51. Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi
    A framework of evolutionary graph generation system and its application to circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:201-204 [Conf]
  52. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
    A zero-time-overhead asynchronous four-phase controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:205-208 [Conf]
  53. Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang
    A new robust handshake for asymmetric asynchronous micro-pipelines. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:209-212 [Conf]
  54. Reza Sedaghat
    A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:213-216 [Conf]
  55. Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh
    Design of a switch for network on chip applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:217-220 [Conf]
  56. S. Wei, K. Shimizu
    Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:221-224 [Conf]
  57. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:225-228 [Conf]
  58. I. Kouretas, Vassilis Paliouras
    High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:229-232 [Conf]
  59. Peter Celinski, Derek Abbott, Sorin Dan Cotofana
    Area efficient, high speed parallel counter circuits using charge recycling threshold logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:233-236 [Conf]
  60. Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
    Virtual-scan: a novel approach for software-based self-testing of microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:237-240 [Conf]
  61. Sanghoon Choi, William R. Eisenstadt, Robert M. Fox
    Design of programmable embedded IF source for design self-test. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:241-244 [Conf]
  62. Daniel Große, Rolf Drechsler
    Formal verification of LTL formulas for SystemC designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:245-248 [Conf]
  63. Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti
    Open computation tree logic with fairness. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:249-252 [Conf]
  64. Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
    Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:253-256 [Conf]
  65. Sang-Dae Shin, Hun Choi, Bai-Sun Kong
    Variable sampling window flip-flop for low-power application. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:257-260 [Conf]
  66. Massimo Alioto, Gaetano Palumbo
    Design of MUX, XOR and D-latch SCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:261-264 [Conf]
  67. Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou
    Parameterized and low power DSP core for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:265-268 [Conf]
  68. Shrutin Ulman
    Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:269-272 [Conf]
  69. Magdy A. El-Moursy, Eby G. Friedman
    Inductive interconnect width optimization for low power. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:273-276 [Conf]
  70. Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu
    On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:277-280 [Conf]
  71. D. S. Hong, Mourad N. El-Gamal
    Low operating voltage and short settling time CMOS charge pump for MEMS applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:281-284 [Conf]
  72. Louie Pylarinos, Khoman Phang
    Analysis of output ripple in multi-phase clocked charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:285-288 [Conf]
  73. Ali Abbasian, S. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
    No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:289-292 [Conf]
  74. Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin
    A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:293-296 [Conf]
  75. Hojun Kim, Jin-Gyun Chung
    Minimizing switching activity in input word by offset and its low power applications for FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:297-300 [Conf]
  76. Kuang-Fu Cheng, Sau-Gee Chen
    A low-complexity correlation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:301-304 [Conf]
  77. Pedro Julián, Andreas G. Andreou, Pablo Sergio Mandolesi, David H. Goldberg
    A low-power CMOS integrated circuit for bearing estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:305-308 [Conf]
  78. Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki
    Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:309-312 [Conf]
  79. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:313-316 [Conf]
  80. Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang
    A novel hybrid pass logic with static CMOS output drive full-adder cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:317-320 [Conf]
  81. Jiangmin Gu, Chip-Hong Chang
    Ultra low voltage, low power 4-2 compressor for high speed multiplications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:321-324 [Conf]
  82. Asim J. Al-Khalili, Aiping Hu
    Design of a 32-bit squarer - exploiting addition redundancy. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:325-328 [Conf]
  83. Yinshui Xia, B. Ali, A. E. A. Almaini
    Area and power optimization of FPRM function based circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:329-332 [Conf]
  84. Anders Berkeman, Viktor Öwall
    A configurable divider using digit recurrence. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:333-336 [Conf]
  85. Pak-Keung Leung, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:337-340 [Conf]
  86. Ahmet T. Erdogan, Tughrul Arslan
    Low power block based FIR filtering cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:341-344 [Conf]
  87. Masayoshi Fujino, Vasily G. Moshnyaga
    Dynamic operand transformation for low-power multiplier-accumulator design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:345-348 [Conf]
  88. Vinita V. Deodhar, Jeffrey A. Davis
    Voltage scaling and repeater insertion for high-throughput low-power interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:349-352 [Conf]
  89. M. Hasan, Tughrul Arslan
    A triple port RAM based low power commutator architecture for a pipelined FFT processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:353-356 [Conf]
  90. Richard C. S. Morling, Izzet Kale, S. J. Morris, F. Custode
    DSP engine for ultra-low-power audio applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:357-360 [Conf]
  91. Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel
    An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:361-364 [Conf]
  92. Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong
    A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:365-368 [Conf]
  93. Jader A. De Lima
    An active leakage-injection scheme applied to low-voltage SRAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:369-372 [Conf]
  94. Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu
    Low-power and low-voltage fully parallel content-addressable memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:373-376 [Conf]
  95. Byung-Do Yang, Lee-Sup Kim
    A low power charge sharing ROM using dummy bit lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:377-380 [Conf]
  96. Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang
    A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:381-384 [Conf]
  97. Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing the locality of memory access patterns by low-overhead hardware address relocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:385-388 [Conf]
  98. Chunhong Chen, Jiang Zhao, Majid Ahmadi
    A semi-Gray encoding algorithm for low-power state assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:389-392 [Conf]
  99. Marek Wróblewski, Matthias Müller, Andreas Wortmann, Sven Simon, Wilhelm Pieper, Josef A. Nossek
    A power efficient register file architecture using master latch sharing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:393-396 [Conf]
  100. Sei Hyung Jang
    A new synchronous mirror delay with an auto-skew-generation circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:397-400 [Conf]
  101. Olivier Thomas, Amara Amara
    An SOI 4 transistors self-refresh ultra-low-voltage memory cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:401-404 [Conf]
  102. Hing-mo Lam, Chi-Ying Tsui
    High performance and low power completion detection circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:405-408 [Conf]
  103. Toshifumi Enomoto, Tomohito Ei
    Low-power CMOS circuit techniques for motion estimators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:409-412 [Conf]
  104. Alberto Nannarelli, Gian-Carlo Cardarilli, Marco Re
    Power-delay tradeoffs in residue number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:413-416 [Conf]
  105. E. Athanasopoulou, Christoforos N. Hadjicostis
    Upper and lower bounds on FSM switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:417-420 [Conf]
  106. Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi
    Exploiting reconfigurability for low-power control of embedded processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:421-424 [Conf]
  107. Kuo-Hsing Cheng, Yung-Hsiang Lin
    A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:425-428 [Conf]
  108. Mircea R. Stan, Marco Barcella
    MTCMOS with outer feedback (MTOF) flip-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:429-432 [Conf]
  109. Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen
    Comparison of synthesized bus and crossbar interconnection architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:433-436 [Conf]
  110. Thomas Olsson, Peter Nilsson
    A digitally controlled PLL for digital SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:437-440 [Conf]
  111. P. C. Chen, James B. Kuo
    Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:441-444 [Conf]
  112. Su Kio, Kian Haur Chong, Carl Sechen
    A low power delayed-clocks generation and distribution system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:445-448 [Conf]
  113. Faisal A. Musa, Anthony Chan Carusone
    Clock recovery in high-speed multilevel serial links. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:449-452 [Conf]
  114. Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
    Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:453-456 [Conf]
  115. Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
    Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:457-460 [Conf]
  116. Renato Fernandes Hentschke, Ricardo Reis
    Plic-Plac: a novel constructive algorithm for placement. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:461-464 [Conf]
  117. Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske
    Graph-based approach to evaluate net routability of a floorplan. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:465-468 [Conf]
  118. Michael A. Soderstrand
    CSD multipliers for FPGA DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:469-472 [Conf]
  119. Andrey V. Mezhiba, Eby G. Friedman
    Electrical characteristics of multi-layer power distribution grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:473-476 [Conf]
  120. Noha H. Mahmoud, Yehea I. Ismail
    Accurate rise time and overshoots estimation in RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:477-480 [Conf]
  121. Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi
    Noise-constrained interconnect optimization for nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:481-484 [Conf]
  122. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    A crosstalk aware two-pin net router. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:485-488 [Conf]
  123. Sarat C. Maruvada, Karthik Krishnamoorthy, Subodh Annojvala, Florin Balasa
    Placement with symmetry constraints for analog layout using red-black trees. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:489-492 [Conf]
  124. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
    Arbitrary convex and concave rectilinear block packing based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:493-496 [Conf]
  125. Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
    General iterative heuristics for VLSI multiobjective partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:497-500 [Conf]
  126. Jyh Perng Fang, Sao Jie Chen
    Tile-graph-based power planning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:501-504 [Conf]
  127. Eun-Gu Jung, Byung-Soo Choi, Dong-Ik Lee
    High performance asynchronous bus for SoC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:505-508 [Conf]
  128. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    Minimizing coupling jitter by buffer resizing for coupled clock networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:509-512 [Conf]
  129. Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
    Statistical modeling of gate-delay variation with consideration of intra-gate variability. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:513-516 [Conf]
  130. M. M. Mansour, Amit Mehrotra
    Efficient core designs based on parameterized macrocells with accurate delay models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:517-520 [Conf]
  131. Chien-In Henry Chen, Kiran George
    Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:521-524 [Conf]
  132. Dun Zhao, Shambhu Upudhyaya
    A resource balancing approach to SoC test scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:525-528 [Conf]
  133. Christoforos N. Hadjicostis
    Aliasing probability calculations in nonlinear compactors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:529-532 [Conf]
  134. Beatriz Olleta, Lance Juffer, Degang Chen, Randall L. Geiger
    A deterministic dynamic element matching approach to ADC testing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:533-536 [Conf]
  135. Kumar L. Parthasarathy, Le Jin, Turker Kuyel, Dana Price, Degang Chen, Randall L. Geiger
    Experimental evaluation and validation of a BIST algorithm for characterization of A/D converter performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:537-540 [Conf]
  136. Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha
    Systematic test program generation for SoC testing using embedded processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:541-544 [Conf]
  137. Aiman H. El-Maleh, Khaled Al-Utaibi
    On efficient extraction of partially specified test sets for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:545-548 [Conf]
  138. Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
    Combinational circuit fault diagnosis using logic emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:549-552 [Conf]
  139. Meng Lieh Sheu, Tai Ping Sun, Chi Wen Lu, Mon Chau Shie
    The fault detection of cross-check test scheme for infrared FPA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:553-556 [Conf]
  140. Alfio Zanchi, Ioannis Papantonopoulos, F. Tsay
    Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:557-560 [Conf]
  141. R. Rashidzadeh, Majid Ahmadi, William C. Miller
    A tester-on-chip implementation in 0.18µ CMOS utilizing a MEMS interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:561-564 [Conf]
  142. Klaus D. Maier
    On-chip debug support for embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:565-568 [Conf]
  143. Massimo Conti, Paolo Crippa, Francesco Fedecostunte, Simone Orcioni, F. Ricciardi, Claudio Turchetti, Loris Vendrame
    A modular test structure for CMOS mismatch characterization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:569-572 [Conf]
  144. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    Efficient BIST schemes for RNS datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:573-576 [Conf]
  145. Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen
    BIST for clock jitter measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:577-580 [Conf]
  146. Kaamran Raahemifar, Majid Ahmadi
    A new initialization technique for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:581-584 [Conf]
  147. Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:585-588 [Conf]
  148. Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet
    Fast prototyping of reconfigurable architectures from a C program. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:589-592 [Conf]
  149. Issam Maalej, Guy Gogniat, Mohamed Abid, Jean Luc Philippe
    Interface design approach for system on chip based on configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:593-596 [Conf]
  150. Karen O. Egiazarian, Jaakko Astola, Radomir S. Stankovic, Milena Stankovic
    Circuit design from optimal wavelet packet series expressions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:597-600 [Conf]
  151. Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
    An Integrated Framework of Design Optimization and Space Minimization for DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:601-604 [Conf]
  152. Rüdiger Ebendt
    Reducing the number of variable movements in exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:605-608 [Conf]
  153. Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir
    A novel improvement technique for high-level test synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:609-612 [Conf]
  154. Vassilis Androutsopoulos, T. J. W. Clarke, Mike Brookes
    Synthesis and optimization of interfaces between hardware modules with incompatible protocols. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:613-616 [Conf]
  155. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
    Control signal sharing of asynchronous circuits using datapath delay information. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:617-620 [Conf]
  156. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Multitasking in hardware-software codesign for reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:621-624 [Conf]
  157. Byoung-Woon Kim, Chong-Min Kyung
    System-on-Chip design using intellectual properties with imprecise design costs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:625-628 [Conf]
  158. Nattawut Thepayasuwan, Hua Tang, Alex Doboli
    An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:629-632 [Conf]
  159. Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong
    A systolic multiplier with LSB first algorithm over GF(2/sup m/) which is as efficient as the one with MSB first algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:633-636 [Conf]
  160. Yonghee Im, Kaushik Roy
    A logic-aware layout methodology to enhance the noise immunity of domino circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:637-640 [Conf]
  161. Wu Jigang, Thambipillai Srikanthan
    Partial rerouting algorithm for reconfigurable VLSI arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:641-644 [Conf]
  162. Mineo Kaneko, Kazuaki Oshio
    Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:645-648 [Conf]
  163. Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
    A fault tolerant hardware based file system manager for solid state mass memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:649-652 [Conf]
  164. Patrice Fleury, Alan F. Murray
    Mixed-signal VLSI implementation of the Products of Experts' contrastive divergence learning scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:653-656 [Conf]
  165. Akira Hirose, Kazuhiko Nakazawa
    Analog continuous-time recurrent decision circuit with high signal-voltage symmetry and delay-time equality. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:657-660 [Conf]
  166. Harish K. Kashyap, Bansilal, P. Arun Koushik
    Hybrid neural network architecture for age identification of ancient Kannada scripts. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:661-664 [Conf]
  167. Hoda S. Abdel-Aty-Zohdy, J. N. Allen, Robert L. Ewing
    Plastic NNs for biochemical detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:665-668 [Conf]
  168. Mohammed A. Hasan
    Algorithms for computating principal and minor invariant subspaces of large matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:669-672 [Conf]
  169. Hongxia Wang, Chen He, Juebang Yu
    Analysis of global exponential stability for a class of bidirectional associative memory networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:673-676 [Conf]
  170. M. Saubhayana, R. W. Newcomb
    Synthesis for symmetric weight matrices of neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:677-680 [Conf]
  171. Changyin Sun, Changgui Sun, Chun-Bo Feng
    Exponential periodicity of neural networks with delays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:681-684 [Conf]
  172. Amine Bermak
    A highly scalable 3D chip for binary neural network classification applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:685-688 [Conf]
  173. Radu Dogaru, Ioana Dogaru, Manfred Glesner
    Compact image compression using simplicial and ART neural systems with mixed signal implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:689-692 [Conf]
  174. QingNian Zhang, XiangYang He, JianQi Liu
    RBF network based on genetic algorithm optimization for nonlinear time series prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:693-696 [Conf]
  175. Ewan Mardhana, Tohru Ikeguchi
    Neurosearch: a program library for neural network driven search meta-heuristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:697-700 [Conf]
  176. G. A. Alencar, Luiz Pereira Calôba, M. S. Assis
    Artificial neural networks as rain attenuation predictors in earth-space paths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:701-704 [Conf]
  177. Giovanni Tummarello, Fabio Nardini, Francesco Piazza
    Stepsize control in NLMS acoustic echo cancellation using a neural network. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:705-708 [Conf]
  178. Hongmei Yan, Jun Zheng, Yingtao Jiang, Chenglin Peng, Qinghui Li
    Development of a decision support system for heart disease diagnosis using multilayer perceptron. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:709-712 [Conf]
  179. Stefano Squartini, Amir Hussain, Francesco Piazza
    Preprocessing based solution for the vanishing gradient problem in recurrent neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:713-716 [Conf]
  180. Jeong-Yon Shim, Lei Xu
    Medical data mining model for oriental medicine via BYY Binary Independent Factor Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:717-720 [Conf]
  181. Sabri Arik
    Global asymptotic stability of a larger class of delayed neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:721-724 [Conf]
  182. Hong Ye, Zhiping Lin
    Global optimization of neural network weights using subenergy tunneling function and ripple search. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:725-728 [Conf]
  183. Adrian Burian, Jarmo Takala
    A recurrent neural network for 1-D phase retrieval. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:729-732 [Conf]
  184. Yigang He, Yanghong Tan, Yichuang Sun
    Class-based neural network method for fault location of large-scale analogue circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:733-736 [Conf]
  185. Kenya Jin'no, Hiroshi Taguchi, Takao Yamamoto, Haruo Hirose
    Dynamical hysteresis neural networks for graph coloring problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:737-740 [Conf]
  186. Thanapant Raicharoen, Chidchanok Lursinsap, Paron Sanguanbhokai
    Application of critical support vector machine to time series prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:741-744 [Conf]
  187. A. Luchetta, C. Serio, M. Viggiano
    A neural network to retrieve atmospheric parameters from infrared high resolution sensor spectra. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:745-748 [Conf]
  188. José A. Calderón-Martínez, Pascual Campoy-Cervera
    A convolutional neural architecture: an application for defects detection in continuous manufacturing systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:749-752 [Conf]
  189. Neyir Ozcan, Sabri Arik, Vedat Tavsanoglu
    New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:753-756 [Conf]
  190. Jonne Poikonen, Ari Paasio
    An area-efficient full-wave current rectifier for analog array processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:757-760 [Conf]
  191. Gianluca Giustolisi, Alessandro Rizzo
    CMOS implementation of an extended CNN cell to deal with complex dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:761-764 [Conf]
  192. Fernando Corinto, Marco Gilli, Pier Paolo Civalleri
    On dynamic behavior of full range CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:765-768 [Conf]
  193. Hyongsuk Kim, Seungwan Hong, Hongrak Son, Tamás Roska, F. Werblin
    High speed road boundary detection on the images for autonomous vehicle with the multi-layer CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:769-772 [Conf]
  194. Radu P. Matei
    Cellular neural networks with second-order cells and their pattern forming properties. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:773-776 [Conf]
  195. P. Barrera, A. Calabro, Luigi Fortuna, D. Porto
    A new method for implementing gate operations in a quantum factoring algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:777-780 [Conf]
  196. Marco Gilli, Paolo Checco, Fernando Corinto
    Periodic orbits and bifurcations in one-dimensional arrays of Chua's circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:781-784 [Conf]
  197. Wasimon Panichpattanakul, Watit Bejapolakul
    Fuzzy power control with weighting function in DS-CDMA cellular mobile communication system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:785-788 [Conf]
  198. Phayung Meesad, Gary G. Yen
    Fuzzy temporal representation and reasoning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:789-792 [Conf]
  199. Maide Bucolo, Luigi Fortuna, Manuela La Rosa
    Synchronization in arrays of fuzzy chaotic oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:793-796 [Conf]
  200. Felix Homburg, Rogelio Palomera-Garcia
    A high speed scalable and reconfigurable fuzzy controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:797-800 [Conf]
  201. Janusz A. Starzyk, Tsun-Ho Liu
    Design of a Self-Organizing Learning Array system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:801-804 [Conf]
  202. Shahed Shahir, Xiang Chen, Majid Ahmadi
    Fuzzy Associative Database for multiple planar object recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:805-808 [Conf]
  203. S. Phimoltares, Chidchanok Lursinsap, Kosin Chamnongthai
    Tight bounded localization of facial features with color and rotational independence. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:809-812 [Conf]
  204. Matteo Perenzoni, Andrea Gerosa, Andrea Neviani
    Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:813-816 [Conf]
  205. Adria Bofill-i-Petit, Alan F. Murray
    Learning temporal correlations in biologically-inspired aVLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:817-820 [Conf]
  206. Hiroomi Hikawa
    Pulse mode neuron with leakage integrator and additive random noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:821-824 [Conf]
  207. Vladimir Brajovic
    Lossless non-arbitrated address-event coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:825-828 [Conf]
  208. Shih-Chii Liu
    A wide-field direction-selective aVLSI spiking neuron. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:829-832 [Conf]
  209. Amine Bermak, Matihias Hojinger
    Focal plane image segmentation using locally interconnected spiking pixel architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:833-836 [Conf]
  210. Dongming Xu, Liping Deng, John G. Harris, José Carlos Príncipe
    Design of a reduced KII set and network in analog VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:837-840 [Conf]
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