Conferences in DBLP
Eby G. Friedman , Sung-Mo Kang , Eric A. Vittoz , David J. Allstot , Erik P. Harris , Ran-Hong Yan Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. [Citation Graph (0, 0)][DBLP ] Conf ] R. X. Gu , Mohamed I. Elmasry An All-N-Logic High-Speed Single-Phase Dynamic CMOS Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Qiuting Huang , Robert Rogenmoser A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Yi Huang , Chung-Yu Wu New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. [Citation Graph (0, 0)][DBLP ] Conf ] K. M. Sharaf , Mohamed I. Elmasry BiCMOS Active-Pull-Down Non-Threshold Logic Cicuits for High-Speed Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yuh-Kuang Tseng , Kuo-Hsing Cheng , Chung-Yu Wu Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Todd C. Weigandt , Beomsup Kim , Paul R. Gray Analysis of Timing Jitter in CMOS Ring Oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Beomsup Kim , Todd C. Weigandt , Paul R. Gray PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Simon , Ernst G. Bernard , Matthias Sauer , Josef A. Nossek A New Retiming Algorithm for Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] V. K. Raj , R. V. Idate , A. W. Booth , M. Botlo , J. Dorenbosch , E. C. Milner , E. M. Wang Design of an ASIC to Implement a New Data Tranfer Protocol for High Energy Physics. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Midtgaard , Christer Svensson 5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Kyung-Wook Shin , Heung-Woo Jeon , Yong-Seum Kang An Efficient VLSI Implementation of Vector-Radix 2-D DCT using Mesh-Connected 2-D Array. [Citation Graph (0, 0)][DBLP ] Conf ] Nianxiong Tan , Sven Eriksson , Lars Wanhammar A Power-Saving Technique for Bit-Serial DSP ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Maher N. Fahmi , Fayez El Guibaly , Sreenivasachar Sunder , Dale J. Shpak Design of Novel Serial-Parallel Inner-Product Processors. [Citation Graph (0, 0)][DBLP ] Conf ] June Wang , Zhongde Wang , Graham A. Jullien , William C. Miller Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Bozena Kaminska , Yvon Savaria Pseudo-Random Vector Compaction for Sequential Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Sarwono Sutikno , Mineo Kaneko , Mahoki Onoda A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Ramaswamy , Wasfy B. Mikhael An Efficient Coding Technique for Multi-Transform Image Representation. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. Jamali , S. Ravindranath , Subhash C. Kwatra , A. G. Eldin ASIC Design of a Generalized Covariance Matrix Processor for DOA Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Vassilis Paliouras , Thanos Stouraitis Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Giacomo Buonanno , Donatella Sciuto , Renato Stefanelli CMOS Reliability Improvements Through a New Fault Tolerant Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Randy E. Bolling , Sami A. Al-Arian Reconfigurable Linear Feedback Register Design, Analysis & Applications. [Citation Graph (0, 0)][DBLP ] Conf ] M. H. Shakiba , David A. Johns , Kenneth W. Martin Analog Implementation of Class-IV Partial-Response Viterbi Detector. [Citation Graph (0, 0)][DBLP ] Conf ] Jaime Ramírez-Angulo , Kevin Treece , Mark DeYong Real Time Solution of Laplace equation using Analog VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] James E. C. Brown , Paul J. Hurst , Lawrence Der , Iskender Agi A Comparison of Analog DFE Architectures for Disk-Drive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Robin Woodburn , H. Martin Reekie , Alan F. Murray Pulse-Stream Circuits for On-Chip Learning in Analogue VLSI Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] A. Baschirotto , M. Bosetti , R. Castello , A. Gola , G. Pessina , P. Rancoita , M. Rattaggi , M. Redaelli , G. Terzi High Speed Monolithic Read-Out System for High Energy Physics Experiments. [Citation Graph (0, 0)][DBLP ] Conf ] Brian S. Cherkauer , Eby G. Friedman Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chong-Gun Yu , Randall L. Geiger An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chii Liu , Carver Mead Continuous-Time Adaptive Delay System. [Citation Graph (0, 0)][DBLP ] Conf ] Diego Vázquez , Adoración Rueda , José L. Huertas A Low-Cost Strategy for Testing Analog Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Vaupel , Heinrich Meyr High Speed FIR-Filter Architectures with Scalable Sample Rates. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Karkada , Chaitali Chakrabarti , Andreas Spanias High Sample Rate Architectures for Block Adaptive Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Hubert Harrer , Josef A. Nossek , Tamás Roska , Leon O. Chua A Current-Mode DTCNN Universal Chip . [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Wei Ku , Liang-Gee Chen , Tzi-Dar Chiueh , Her-Ming Jong Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Klass , Michael J. Flynn , A. J. van de Goor A 16x16-bit Static CMOS Wave-Pipelined Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Ren-Yang Yang , Chen-Yi Lee High-Throughput Data Compressor Designs Using Content Addressable Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Karel Adriaensen , Pascal Roobrouck Synchronous Traffic to Asynchronous Switch-Fabric Shaper. [Citation Graph (0, 0)][DBLP ] Conf ] An-Yeu Wu , K. J. Ray Liu A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. [Citation Graph (0, 0)][DBLP ] Conf ] Osama T. Albaharna , Peter Y. K. Cheung , Thomas J. Clarke Virtual Hardware and the Limits of Computational Speed-up. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Burleson , L. W. Cotten , Fabian Klass , Maciej J. Ciesielski Forum: Wave-pipelining: Is it Practical? [Citation Graph (0, 0)][DBLP ] Conf ] Sheng-Chieh Huang , Liang-Gee Chen , Thou-Ho Chen The Chip Design of A 32-b Logarithmic Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Zen Shen , Yi-Hsin Tao , Lan-Rong Dung On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Neves , Eby G. Friedman Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Kim , Sung-Mo Kang , Sachin S. Sapatnekar High Performance CMOS Macromodule Layout Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Paul-Waie Shew , Jin-Tai Yan , Pei-Yung Hsiao , Yong-Ching Lim Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Sreekrishna Madhwapathy , Naveed A. Sherwani , Siddharth Bhingarde , Anand Panyam An Efficient Four Layer Over-the-Cell Router. [Citation Graph (0, 0)][DBLP ] Conf ] Pramod Anne , Aditya Reddy , Naveed A. Sherwani , Anand Panyam , Siddharth Bhingarde Comparative Analysis of New CMOS Leaf Cells for OTC Routing. [Citation Graph (0, 0)][DBLP ] Conf ] H. J. Kadim , G. E. Taylor Logic Value Assignment Contribution to Testability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sami A. Al-Arian , Randy E. Bolling Improving the Testability of VLSI Circuits through Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Shyue-Win Wei VLSI Architectures for Computing Exponentiations, Multiplicative Inverses, and Divisions in GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Lori Lucke , Chaitali Chakrabarti A Digit-Serial Architecture for Gray-Scale Morphological Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Jongseob Baek , Seunghyun Nam , Moonkey Lee , Chuldong Oh , Kisoo Hwang A Fast Array Architecture for Block Matching Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Gagan Gupta , Chaitali Chakrabarti VLSI Architectures for Hierarchical Block Matching. [Citation Graph (0, 0)][DBLP ] Conf ] P. Planet , G. Privat Convergence Control of Relaxation Processes with Fine-Grain Locally-Connected Two-Scale Automata Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal Nourji , Nicolas Demassieux Optimization of Real-Time VLSI Architectures for Distributed Arithmetic-Based Algorithms: Application to HDTV Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson L. Passos , Edwin Hsing-Mean Sha , Steven C. Bass Partitioning and Retiming of Multi-Dimensional Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Sagishima , Kozo Kimura , Hiroaki Hirata , Tokuzo Kiyohara , Shigeo Asahara , Takao Onoye , Isao Shirakawa Multi-Threaded Processor for Image Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-In Guo , Chi-Min Liu , Chein-Wei Jen A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Ping-Tsung Wang , Kun-Nen Chen , Yen-Tai Lai A High Performance FPGA with Hierarchical Interconnection Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen P. S. Lam A 21 /2 -Dimensional Systolic Array Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Shalini Yajnik , Niraj K. Jha Synthesis of Fault Tolerant Architectures for Molecular Dynamics. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Duc , Didier Nicoulaz , Daniel Mlynek A RISC Controller with Customisation Facility for Flexible System Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Maini Williams , Jari Nurmi Multipurpose Chip for Physiological Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Nianxiong Tan , Sven Eriksson , Lars Wanhammar A Novel Bit-Serial Design of Comb Filters for Oversampling A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew G. Dempster , Malcolm D. Macleod Use of Multiplier Blocks to Reduce Filter Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] A. Tawfik , Fayez El Guibaly , Panajotis Agathoklis VLSI Array Processors Implementation of Block-State IIR Digital Filtentrs. [Citation Graph (0, 0)][DBLP ] Conf ] Evaggelinos P. Mariatos , D. E. Metafas , John Ant. Hallas , Constantinos E. Goutis A Fast DCT Processor, Based on Special Purpose CORDIC Rotators. [Citation Graph (0, 0)][DBLP ] Conf ] Erik De Man , Matthias Schöbinger , Tobias G. Noll , Georg Sebald A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators. [Citation Graph (0, 0)][DBLP ] Conf ] C. T. Clark , Graham R. Nudd , S. Summerfield Current Mode Techniques for Multiple Valued Arithmetic and Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Marek J. Patyra , John E. Long Synthesis of Current Mode Building Blocks for Fuzzy Logic Control Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bracey , William Redman-White , J. B. Hughes A Switched-Current Sigma Delta Converter for Direct Photodiode Interfacing. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Renaudin , Bachar El Hassan The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Wen Wu , Yung-Fa Chou General Modular Multiplication by Block Multiplication and Table Lookup. [Citation Graph (0, 0)][DBLP ] Conf ] Jack L. Meador , Paul Hylander A Pulse Coded Winner-Take-All Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] D. Schin , Yinan N. Shen , Fabrizio Lombardi An Approach for UIO Generation for FSM Verification and Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian T. J. Fenn , David Taylor , Mohammed Benaissa A Dual Basis Systolic Divider for GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Hosahalli R. Srinivas , Keshab K. Parhi A Fast Radix-4 Division Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Weinan Gao , W. Martin Snelgrove Floating Gate Charge-Sharing: a Novel Circuit for Analog Trimming. [Citation Graph (0, 0)][DBLP ] Conf ] Daejong Kim , Jaejin Park , Sungjoon Kim , Deog-Kyoon Jeong , Wonchan Kim A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. [Citation Graph (0, 0)][DBLP ] Conf ] James B. Kuo , K. W. Su , J. H. Lou A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ali El-Zein , Monjurul Haque , S. Chowdhury Simulating Nonuniform Lossy Lines with Frequency Dependent Parameters by the Method of Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Monjurul Haque , Ali El-Zein , S. Chowdhury Transient Simulation of Nonuniform Transmission Lines by Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] P. Zhou , J. C. Czilli , Graham A. Jullien , William C. Miller Current Input TSPC Latch for High Speed, Complex Switching Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Tobi Delbrück , Carver Mead Adaptive Photoreceptor with Wide Dynamic Range. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Nekili , Yvon Savaria , Guy Bois A Fast Low-Power Driver for Long Interconnections in VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sameh Ghannoum , Dmitri Chtchvyrkov , Yvon Savaria A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Golshan , Baher Haroun A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Low Power CMOS Clock Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Yvon Savaria , Dmitri Chtchvyrkov , John F. Currie A Fast CMOS Voltage-Controlled Ring Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Iulian B. Ciocoiu Circuit Implementation of a Nonmonotone Activation Function. [Citation Graph (0, 0)][DBLP ] Conf ] 