Conferences in DBLP
Bo Zhang , Montgomery Goodson , Richard Schreier Invariant Sets for General Second-Order Lowpaws Delta-Sigma Modulators with DC Inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Lindberg Sinusoidal Excitation on the Chua's Circuit Simulation of Limit Cycles and Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Fries Simulatikon of One-Dimensional Euler-Flow by Means of Multidimensional Wave Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick A. Littlehales , Christopher P. Lewis , Steven R. Bishop Dynamic Characteristics of a Digital Transducer. [Citation Graph (0, 0)][DBLP ] Conf ] Kristina Kutzer , Wolfgang M. Schwarz , Anthony C. Davies Chaotic Signals Generated by Digital Filter Overflow. [Citation Graph (0, 0)][DBLP ] Conf ] Kenya Jin'no , Toshimichi Saito Dynamics of a Simple Hysteresis Network. [Citation Graph (0, 0)][DBLP ] Conf ] Jaromír Brzobohaty , Jirí Pospísil , Zdenek Kolka Decomposed Parametric Form of the State Model of a Piecewise-Linear System. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Arena , Luigi Fortuna , Maria Gabriella Xibilia Predicting Complex Chaotic Time Series via Complex Valued MLPs. [Citation Graph (0, 0)][DBLP ] Conf ] Pere Palà-Schönwälder , J. M. Miró Sans A Discrete-Time Equivalent System Approach to the Periodic Response of Nonlinear Autonomous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] K. M. Cheung , S. F. Yau A Novel Method in Compensating Random Perturbations in Eigen-Based Subspace Method. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Iordache , Razvan Iordache Generalized Diakoptic Analysis for Large-Scale Piecewise-Linear Nonlinear Electircal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zdenek Kolka , Jirí Pospísil Algorithms for the Automatic Design of the Decomposed state Model of an One-Dimensional Piecewise-Linear System. [Citation Graph (0, 0)][DBLP ] Conf ] Vaithianathan Venkatasubramanian , Heinz Schättler , John Zaborszky A Time-Delay Differential-Algebraic Phasor Formulation of the Large Power System Dynamics. [Citation Graph (0, 0)][DBLP ] Conf ] A. Bagchi , K. A. Clements , P. W. Davis , F. H. Maurais A Comparison of Algorithms for Least Absolute Value State Estimation in Electoric Power Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Mori , Junya Kanno A Method for Evaluating a Mapping Parameter for Power System Dynamic Stability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Marian K. Kazimierczuk , Robert Cravens II , Alberto Reatti Closed-Loop Input Impedance of PWM Buck-Derived DC-DC Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Irwin W. Sandberg An Algorithm for Solving the Equations of Monotone Nonlinear Resistive Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Xie-Ting Ling , Yih-Fang Huang , Ruey-Wen Liu A Neural Network for Blind Signal Separation. [Citation Graph (0, 0)][DBLP ] Conf ] A. Namdar , B. H. Leung Quantization Noise of 1-Bit Double-Loop Sigma-Delta Modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Hari C. Reddy , George S. Moschytz Studies on the Stability of Two Dimsensional Analog Nonlinear Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Toshimichi Saito , Kunihiko Mitsubori Rigorous and Realistic Control of Piecewise Linear Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé Dedieu , Maciej Ogorzalek A Simple and Robust Method for Controlling Chaotic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Itoh , Hiroyuki Murakami , Leon O. Chua Controlling Chaotic Motions in Chua's Circuit via Tunnels. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Mackenzie , Mark B. Sandler Modelling Sound with Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihiko Horio , Ken Suyama IC Implementation of Switched-Capacitor Chaotic Neuron. [Citation Graph (0, 0)][DBLP ] Conf ] Orla Feely Nonlinear Dynamics of Chaotic Double-Loop Sigma Delta Modulation. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Itoh , Hiroyuki Murakami , Leon O. Chua Performance of Yamakawa's Chaotic Chips and Chua's Circuits for Secure Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshifumi Nishio , Akio Ushida Multimode Chaos in Two Coupled Chaotic Oscillators with Hard Nonlinearities. [Citation Graph (0, 0)][DBLP ] Conf ] Kunihiko Mitsubori , Toshimichi Saito Torus Doubling and Hyperchaos in a Five Dimensional Hysteresis Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. Augusto , C. F. B. Almeida New Algorithms in Piecewise Linear Resistive Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Akio Ushida Analysis of Bifurcation Points of Nonlinear Resistive Circuits by Curve Tracing Method. [Citation Graph (0, 0)][DBLP ] Conf ] J. T. Bean , P. J. Langlois A Current Mode Analog Circuits for Tent Maps Using Piecewise Linear Functions. [Citation Graph (0, 0)][DBLP ] Conf ] S. W. Ng A Variable Dimension Newton Method. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan A. Maio , Flavio G. Canavero Lossy Transmission Line Response via Numerical Laplace Transform Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Denise Wolf , Seth Sanders Multi-Parameter Homotopy Methods for Finding Periodic Solutions of Nonlinear Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joerg Schaepperle , Ernst Lüder Optimization of Distributed Parameter Systems with a Combined Statisitcal-Deterministic Method. [Citation Graph (0, 0)][DBLP ] Conf ] Kari-Pekka Estola , Risto Suoranta Hybrid Multivariate Marginal Median Filters. [Citation Graph (0, 0)][DBLP ] Conf ] P. Debie , R. Coppoolse , K. De Kesel , Peter Van Daele , J. Vandewege , L. Martens Design and Characterization of an Integrated Optical Switch Driver Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Kim Fung Tsang , G. B. Morgan , P. C. L. Yip , Wing Shing Chan Power Oscillator Design: Class E. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Fossas , Josep M. Olm Generation of Signals in a Buck Converter with Sliding Mode Contol. [Citation Graph (0, 0)][DBLP ] Conf ] José Silva Matos , João Canas Ferreira , Ana C. Leão , José M. Silva An Approach to Testability Improvement of Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Xing Dong Jia , Richard M. M. Chen Design and Simulation of Nonlinear Switched Capacitor Autonomous Circuits Containing Nonlinear Active Resistor. [Citation Graph (0, 0)][DBLP ] Conf ] X. Zeng , P. Bowron , A. A. Muhieddine HD and IMD Prediction Techniques for Active Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Jaromír Brzobohaty , Jirí Pospísil , Stanislav Hanus Explicit Circuit Models of Multi-Dimensional Piecewise-Linear Networks. [Citation Graph (0, 0)][DBLP ] Conf ] P. A. Ramamoorthy , Aleksandar Zavaljevski Application of Passive Nonlinear Network Concept in Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Yamauchi , Toshimasa Watanabe An Approximation Algorithm for the Legal Firing Sequence Problem of Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] John McNeill Low Power Circuit Techniques for Generating Kilovolt "Staircase" Waveforms. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Krzyzak , Rolf Unbehauen On Estimation of Nonlinear Systems by Nonparametric Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Arturo Sarmiento-Reyes , Jan Davidse , E. Kleihorst , Arthur H. M. van Roermund A Partitioning-based Method to Determine the Uniqueness of the DC Operating Points of Transistor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Paul , Knut Hüper , Josef A. Nossek On the Geometrical Structure of Network Equations. [Citation Graph (0, 0)][DBLP ] Conf ] John McNeill Jitter in Ring Oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Kanasugi , Seiichiro Moro , Yoshifumi Nishio , Shinsaku Mori On the Synchronization of Oscillators Coupled by One Negative Resistor. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico F. Calandra , Antonino M. Sommariva Influecne of the Drive-Signal Resonant Overtone on Subharmonic Injection-Locking Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Seiichiro Moro , Yoshifumi Nishio , Shinsaku Mori Synchronization Phenomena in RC Oscillators Coupled by One Resistor. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Chien Lee , José Pineda de Gyvez Single-Layer CNN Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Mark P. Joy , Vedat Tavsanoglu Perturbations of CNNs. [Citation Graph (0, 0)][DBLP ] Conf ] Sungjun Park , Seung-Jai Min , Soo-Ik Chae Stereo Correspondence with Discrete-Time Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] John Willis , José Pineda de Gyvez Behavioral Testing of Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] S. Collins , G. F. Marshall , D. R. Brown An Analog Radial Basis Function Circuit Using a Compact Euclidean Distance Calculator. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Francois Crespo , Pierre Lavoie , Yvon Savaria Fast Convergence with Low Precision Weights in ART1 Networks. [Citation Graph (0, 0)][DBLP ] Conf ] M. Forti , A. Liberatore , Stefano Manetti , Mauro Marini On Absolute Stability of Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yukio Kumagai Exact Data Retrieval of Associative Memory with Further Reduced Cross Talk. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Graupe , Hubert Kordylewski Neural Network Control of FES in Paraplegics for Patient-Responsive Ambulation. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw Osowski , Than Vu Quang Multilayer Neural Network Structures as Volterra Filter. [Citation Graph (0, 0)][DBLP ] Conf ] James Donald , Lex A. Akers Pattern Recognition and System Control with a Neural Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yasutami Chigusa , Kensuke Suzuki , Mamoru Tanaka An Image Binarization and Reconstruction with Resistive Network. [Citation Graph (0, 0)][DBLP ] Conf ] Wahid Ahmed , Donald M. Hummels , Mohamad T. Musavi Adaptive RBF Neural Network in Signal Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jenn-Shiang Lai , Sy-Yen Kuo , Ing-Yi Chen Neural Networks for Optimization Problems in Graph Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Acciani , Ernesto Chiarantoni , M. Minenna A New Non Competitive Unsupervised Neural Network for Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Jay Heeb , Lex A. Akers A Temporal Neural System. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Tanaka , Miotsuhiko Awata Extraction of Depth Information by Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Alan F. Murray , Igor Aleksander , Andreas G. Andreou , Misha Mahowald Analogue and Digital Neural VLSI: Duet or Duel? [Citation Graph (0, 0)][DBLP ] Conf ] Martin Hasler , Leon O. Chua , Josef A. Nossek , Ángel Rodríguez-Vázquez , Tamás Roska , Joos Vandewalle Cellular Neural Networks: the Analogic Microprocessor? [Citation Graph (0, 0)][DBLP ] Conf ] Sheng Lin , Qin-Ye Yin Searching over DOA Parameter Space via Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jerzy Rutkowski A Two-Stage Neural Network DC Fault Dictionary. [Citation Graph (0, 0)][DBLP ] Conf ] Yiren Chu , Iuri Mehr , Terry Sculley High Speed Analog Filtering Using Feedforward Neural Network Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Arena , Luigi Fortuna , Luigi Occhipinti , Maria Gabriella Xibilia Neural Networks for Quaternion-valued Function Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhisa Kanaya , Gui-Xin Cheng , Kouichiro Watanabe , Mamoru Tanaka Shortest Path Searching for the Robot Walking Using an Analog Resistive Network. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Kawaguchi , Tatsuya Setoguchi A Neural Network Approach for 3-D Object Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Wang A Recurrent Neural Network for Solving the Shortest Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Cao , Majid Ahmadi , Malayappan Shridhar Handwritten Numeral Recognition with Multiple Features andd Multistage Classifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Joonho Lim , Eel-Wan Lee , Soo-Ik Chae Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] James B. Kuo , B. Y. Chen , Mark W. Mao A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Faramarz Valafar , Okan K. Ersoy PNS Modules for the Synthesis of Parallel Self-Organizing Hierarchical Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Juei Wu A Conceptual Associative Memory with Full Memory Capacity and Ability to Associate Arbitrary Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Hon Keung Kwan , Chuan Zhang Tang A Multilayer Feedforward Neural Network Model for Digital Hardware Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Misha Mahowald Analog VLSI Chip for Stereocorrespondence. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. Holmes , Stephen Churcher , J. Hajto , Alan F. Murray , M. J. Rose Design of Analogue Synapse Circuits using Non-Volatile a-Si:H Memory Devices [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Kui Yang , Ezz I. El-Masry A CMOS Current-Mode PWM Technique for Analog Neural Network Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] D. Gobovic , Mona E. Zaghloul Analog Cellular Neural Network with Application to Artial Differential Equations with Variable Mesh-Size. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio J. Montalvo , Ronald S. Gyurcsik , John J. Paulos Building Blocks for a Temperature-Compensated Analog VLSI Neural Network with On-Chip Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Kinget , Michiel Steyaert Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable Templates. [Citation Graph (0, 0)][DBLP ] Conf ] Shanti S. Vedula , Fathi M. A. Salam , Gamze Erten Subthreshold Analog Circuit for Computing the Maximum Principal Component of 3-D Data. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffrey B. Jackson , Alister Hamilton , Alan F. Murray Pulse Stream VLSI Neural Systems: Into Robotics. [Citation Graph (0, 0)][DBLP ] Conf ] G. Moon , Mona E. Zaghloul , R. W. Newcomb CMOS Design of Two Winner-Take-All Circuits Using Pulse Duty Cycle Synaptic Weighting. [Citation Graph (0, 0)][DBLP ] Conf ] Kegin Gao , M. Omair Ahmad , M. N. S. Swamy A Simple Neural Learning Algorithm for Total Least-Squares Adaptive Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Pitas , Constantine Kotropoulos , Nikos Nikolaidis , Ruikang Yang , Moncef Gabbouj A Class of Order Statistics Learning Vector Quantizers. [Citation Graph (0, 0)][DBLP ] Conf ] Rui J. P. de Figueiredo Neural Modeling & Identification of Nonlinear Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sheng Lin , Qin-Ye Yin Performance Analysis of Hopfield Neural Networks for DOA Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Ray-I Chang , Pei-Yung Hsiao Arabitrarily Shaped Cell Placement by Three-Layer Self-Organizing Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksander Malinowski , Jacek M. Zurada , Peter B. Aronhime Minimal Training Set Size Estimation for Neural Network-Based Function Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Chien Lee , José Pineda de Gyvez Time-Mulitplexing CNN Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Gui-Xin Cheng , Mamoru Tanaka Structural Pattern Compression and Recognition by Linear CNN. [Citation Graph (0, 0)][DBLP ] Conf ] Majid M. Altuwaijri , Magdy A. Bayoumi Arabic Text Recognition Using Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Saida Benromdhane , Fathi M. A. Salam Computationally-improved Optimal Filtering for Supervised Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Sa Hyun Bang , Bing J. Sheu , Josephine C.-F. Chang Search of Optimal Solutions in Multi-Level Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Diamantini , Arnaldo Spalvieri Certain Facts about Kohonen's LVQ1 Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] KyungMin Na , JaeYeol Rheem , SouGuil Ann A Discriminative Training Algorithm for Predictive Neural Network Models. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Deller Jr. , S. D. Hunt Faster, Higher-Quality Training of Feedforward Neural Network Models. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbing Zhu , Mamoru Sasaki , Fumio Ueno , Takahiro Inoue An Appraoch of Sequential-Like Parallel Algorithm in Boltzmann Machine. [Citation Graph (0, 0)][DBLP ] Conf ] F. Mekuria , T. Fjällbrant An Adaptive Neural Network VQ Algorithm and Its Implementation on the DSP32C Signal Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jacek M. Zurada , Aleksander Malinowski , Ian Cloete Sensitivity Analysis for Minimization of Input Data Dimension for Feedforward Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] John G. Elias , David P. M. Northmore , Samer M. Meshreki Wide-Range Variable Dynamics Using Switched-Capacitor Neuromorphs. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut Hilmi Erdem , Yusuf Ozturk Man: Mass Attraction Network. [Citation Graph (0, 0)][DBLP ] Conf ] Cesare Alippi , Vincenzo Piuri , Mariagiovanna Sami Sensitivity to Errors in Artificial Neural Networks: a Behavioural Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Hikaru Mizutani The Back Propagation Method for CNN. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Kou R. Yu , Sze-Fong Yau Solution of the Missing Cure Problem by Artificial Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Jai Min , Eel-Wan Lee , Soo-Ik Chae A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. [Citation Graph (0, 0)][DBLP ] Conf ] Valentina Salapura Neural Networks Using Bit Stream Arithmetic: a Space Efficient Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] David Grant , John Taylor , Paul Houselander A High-Speed Integrated Hamming Neural Classifier. [Citation Graph (0, 0)][DBLP ] Conf ] Joongho Choi , Bing J. Sheu , Josephine C.-F. Chang A Gaussian Synapse Circuit for Analog VLSI Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Paasio , Kari Halonen , Veikko Porra CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients. [Citation Graph (0, 0)][DBLP ] Conf ] Cesare Alippi , Luciano Briozzo Setting and Validating Precision Requirements in the Digital VLSI Implementation of a Neural Defect-Identifier for Machined Objects. [Citation Graph (0, 0)][DBLP ] Conf ] S. Pammu , Steven F. Quigley An Analogue CMOS Defuzzication Circuit with Representation of Triangular Membership Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Delgado-Restituto , Ángel Rodríguez-Vázquez CMOS Current-Mode Chaotic Neurons. [Citation Graph (0, 0)][DBLP ] Conf ] Hwa-Joon Oh , Fathi M. A. Salam Analog CMOS Implementation of Neural Network for Adaptive Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] 