The SCEAS System
Navigation Menu

Conferences in DBLP

IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
1993 (conf/iscas/1993-3)

  1. Eby G. Friedman
    Clock Distribution Design in VLSI Circuits. An Overview. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1475-1478 [Conf]
  2. P. R. Mukund, V. Mukund, Charles E. Noon
    Signal Routing with Temporal Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1479-1482 [Conf]
  3. Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
    Integration of Clock Skew and Register Delays into a Retiming Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1483-1486 [Conf]
  4. Takayasu Sakurai
    High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1487-1490 [Conf]
  5. Razak Hossain, Leszek D. Wronski, Alexander Albicki
    Double Edge Triggered Devices: Speed and Power Considerations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1491-1494 [Conf]
  6. Tam Anh Chu
    On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1495-1498 [Conf]
  7. Abdel-Fattah Yousif, Jun Gu
    An Efficient Global Search Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1499-1502 [Conf]
  8. Weitong Chuang, Ibrahim N. Hajj
    Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1503-1506 [Conf]
  9. Antonio Lioy, Massimo Poncino
    On the Resetability of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1507-1510 [Conf]
  10. Soo Young Lee, Kewal K. Saluja
    Efficient Test Vectors for ISCAS Sequential Benchmark Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1511-1514 [Conf]
  11. Cheng-Juei Wu, Wen-Ben Jone
    On Multiple Fault Detection of Parity Checkers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1515-1518 [Conf]
  12. Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu
    Functional Text Pattern Generation for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1519-1522 [Conf]
  13. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Functional Testing and Constrained Synthesis of Sequential Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1523-1526 [Conf]
  14. Bernd K. Koch, Klaus D. Müller-Glaser
    An Examination of Feedback Bridging Faults in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1527-1530 [Conf]
  15. Dae-Hyung Cho, S. M. Kang
    An Accurate AC Characteristic Table Look-up Model for VLSI Analog Circuits Simulation Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1531-1534 [Conf]
  16. Chang-hoon Choi, Jin-Kyu Park, Yeong-Gil Kim, Kyung-Ho Kim, Sang-Hoon Lee
    New Model Parameter Extraction Environment for the Submicron Circuit Models. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1535-1538 [Conf]
  17. Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross
    An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1539-1542 [Conf]
  18. J. Richard Griffith, Qi-Jun Zhang, Michel S. Nakhla
    Parallel Time Domain Analysis and Optimization of Distributed VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1543-1546 [Conf]
  19. Dimitri Kuznetsov, José E. Schutt-Ainé
    Difference Model Approach for the Transient Simulation of Transmission Lines. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1547-1550 [Conf]
  20. Corneliu A. Marinov, Pekka Neittaanmäki
    Bounds for Distributed Parameter Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1551-1554 [Conf]
  21. Nebil Tanzi, Thomas T. Y. Wong
    Computer-aided Sensitivity Analysis of Transistor Microwave Oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1555-1558 [Conf]
  22. Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi
    Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1559-1562 [Conf]
  23. Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu
    An Expandable Chip Desing for Gray-scale Morphological Operations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1563-1566 [Conf]
  24. Jue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen
    Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1567-1570 [Conf]
  25. Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
    A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1571-1574 [Conf]
  26. Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
    A Multi-phase Shared Bus Structure for the Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1575-1578 [Conf]
  27. Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu
    A High Throughput-Rate Architecture for 8*8 2-D DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1578-1590 [Conf]
  28. Emmanuel Boutillon, N. Demassieux
    A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1579-1582 [Conf]
  29. Klaus Gaedke, Jens Franzen, Peter Pirsch
    A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1583-1586 [Conf]
  30. Matthias Sauer, Ernst G. Bernard, Josef A. Nossek
    Block Sequential CORDIC Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1591-1594 [Conf]
  31. João C. Vital, José E. Franca, Nuno S. Silva
    Fully-digital Testability of a High-speed Conversion System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1595-1598 [Conf]
  32. M. F. Toner, Gordon W. Roberts
    Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1599-1602 [Conf]
  33. Maria J. Avedillo, José M. Quintana, José L. Huertas
    Easily Testable PLA-based FSMS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1603-1606 [Conf]
  34. Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson
    On the Performance of Augmented Signature Testing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1607-1610 [Conf]
  35. Mohamed Jamoussi, Bozena Kaminska
    A Functional-level Testability Evaluation Using a New M-Testability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1611-1614 [Conf]
  36. Chiyuan Chang, Chauchin Su
    A Universal BIST Methodology for Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1615-1618 [Conf]
  37. Naim Ben Hamida, Bozena Kaminska, Yvon Savaria
    Initiability: A Measure of Sequential Testability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1619-1622 [Conf]
  38. Kaushik Roy
    On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1623-1626 [Conf]
  39. Jiri Vlach, Ajoy Opal, Jacek Wojciechowski
    Simulation of Networks with Inconsistent Initial Conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1627-1630 [Conf]
  40. H. Song, Dileep A. Divekar, L. Mills, P. Wang
    A Method for Improving the Efficiency of Simulating Large Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1631-1634 [Conf]
  41. Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
    Efficient and Robust Path Tracing Algorithm for DC Convergence Problem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1635-1638 [Conf]
  42. Lena Peterson, Sven Mattisson
    Dynamic Partitioning for Concurrent Waveform Relaxation-based Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1639-1642 [Conf]
  43. Shawki Areibi, Anthony Vannelli
    Circuit Partitioning Using a Tabu Search Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1643-1646 [Conf]
  44. Tadashi Matsumoto, Tetsuya Sakabe, Kohkichi Tsuji
    On Parallel Symbolic Analysis of Large Networks and Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1647-1650 [Conf]
  45. Marwan Hassoun, Prakash Atawale
    Hierarchical Symbolic Cirucit Analysis of Large-scale Networks on Multi-processor Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1651-1654 [Conf]
  46. Roman V. Dmytryshyn
    The Use of Symbolic-numerical Methods for Electronic Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1655-1657 [Conf]
  47. Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai
    A Performance-driven Approach to the High-level Synthesis of DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1658-1661 [Conf]
  48. Ching-Yi Wang, Keshab K. Parhi
    Loop List Scheduler for DSP Algorithms under Resource Consraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1662-1665 [Conf]
  49. Said Amellal, Bozena Kaminska
    Scheduling of a Control and Data Flow Graph. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1666-1669 [Conf]
  50. William Robertson, S. Periyalwar, William J. Phillips
    RTL Synthesis for Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1670-1673 [Conf]
  51. Samir Lejmi, Bozena Kaminska, Edouard Wagneur
    Resynthesis and Retiming of Synchronous Sequential Cirucits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1674-1677 [Conf]
  52. Michael R. Rhinehart, John A. Nestor
    SALSE II: A Fast Transformational Scheduler for High-level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1678-1681 [Conf]
  53. Ian G. Harris, Alex Orailoglu
    Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1682-1685 [Conf]
  54. Ruchir Puri, Jun Gu
    Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1686-1689 [Conf]
  55. Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
    Efficient Variable Ordering Heuristics for Shared ROBDD. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1690-1693 [Conf]
  56. Bogdan J. Falkowski
    An Algorithm for the Calculation of Generalized Walsh Transform of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1694-1697 [Conf]
  57. Bogdan J. Falkowski
    Calculation of Rademacher-Walsh Spectral Coefficients for Systems of Completely and Incompletely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1698-1701 [Conf]
  58. S. Summerfield
    Design Methodology of VLSI with Multiple Valued Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1702-1705 [Conf]
  59. Chauchin Su, Jyrghong Wang
    ECCSyn: a Synthesis Tool for ECC Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1706-1709 [Conf]
  60. Elizabeth J. Brauer, Sung-Mo Kang
    Functional Verification of ECL Circuits Including Voltage Regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1710-1713 [Conf]
  61. Michael Ogbonna Esonu, Dhamin Al-Khalili, Come Rozon
    Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1714-1717 [Conf]
  62. Ion Constatin Tesu, Florentin Dartu
    Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1718-1721 [Conf]
  63. Xiaqi Liu, Hong Fan
    A Spatial Schur Type LS Algorithm and Its Pyramid Systolic Array Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1722-1725 [Conf]
  64. Scott T. Campbell, Soon Myoung Chung
    Video Decimator Design Using A Systolic Array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1726-1729 [Conf]
  65. Haris M. Stellakis, Elias S. Manolakos
    Time- and Order-recursive Estimation of Higher Order Moments in a Linear Array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1730-1733 [Conf]
  66. Keshab K. Parhi, Takao Nishitani
    Folded VLSI Architectures for Discrete Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1734-1737 [Conf]
  67. Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis
    A Systematic Methodology for Designing Multilevel Systolic Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1738-1741 [Conf]
  68. Jiann-Jenn Wang, Chein-Wei Jen
    A High Throughput Systolic Design for QR Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1742-1745 [Conf]
  69. L. Wang, Iiro Hartimo
    Systolic Array for 2-D Circular Convolution Using the Chinese Remainder Theorem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1746-1749 [Conf]
  70. Peter Pirsch, W. Gehrke, R. Hoffer
    A Hierarchical Multiprocessor Achitecture for Video Coding Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1750-1753 [Conf]
  71. Nobuyuki Yagi, Kazuo Fukui, Kazumasa Enami, Nobuyuki Sasaki, Hidetaka Saitou, Yuji Konno, Ryuichiro Tomita
    A Programmable Video Signal Multi-processor for HDTV Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1754-1757 [Conf]
  72. Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa
    A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1758-1761 [Conf]
  73. Kai Wang, Wai-Kai Chen
    A Class of Zero Wasted Area Floorplan for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1762-1765 [Conf]
  74. S. C. Prasad, P. W. Kollaritsch, P. Anirudhan, D. K. Hwang, S. Lusky, R. Farrow
    Efficient Floorplan Enumeration Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1766-1769 [Conf]
  75. Nasir-ud-Din Gohar, Peter Y. K. Cheung
    A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1770-1773 [Conf]
  76. Cheng-Hsi Chen, Ioannis G. Tollis
    A Fast Parallel Algorithm for Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1774-1777 [Conf]
  77. Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
    A Graph Partitioning Problem for Multiple-chip Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1778-1781 [Conf]
  78. Malgorzata Chrzanowska-Jeske, S. Goller, I. Schafer
    An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1782-1785 [Conf]
  79. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Feasible Region Approximation Using Convex Polytopes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1786-1789 [Conf]
  80. Xiao XiangMing, Robert Spence
    Speeding Design Centering By Reusing Simulated Data. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1790-1792 [Conf]
  81. Richard M. M. Chen, Wilson W. Chan
    An Efficient Tolerance Design Procedure for Yield Maximization Using Optimzation Techniques and Neural Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1793-1796 [Conf]
  82. Yeong-Gil Kim, Jai-Hoon Lee, Kyung-Ho Kim, Sang-Hoon Lee
    SENSATION: A New Environment for Automatic Circuit Optimization and Statistical Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1797-1801 [Conf]
  83. Hua Su, Mohammed Ismail, Christopher Michael
    Yield Optimzation of Analog MOS Integrated Including Transistor Mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1801-1804 [Conf]
  84. Jian Chen, M. A. Styblinski
    A Systematic Approach of Statistical Modeling and Its Application to CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1805-1808 [Conf]
  85. Ming Qu, M. A. Styblinski
    A Heursitsic Global Optimization Algorithm and Its Application to CMOS Circuit Variability Minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1809-1812 [Conf]
  86. B. R. S. Rodrigues, M. A. Styblinski
    Adaptive Hierarchical Multi-objective Fuzzy Optimization for Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1813-1816 [Conf]
  87. Min C. Park, Bang W. Lee, Gwang Moon Kim, Dong H. Kim
    Compact and Fast Multiplier Using Dual Array Tree Structure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1817-1820 [Conf]
  88. Seon Wook Kim, Thanos Stouraitis, Alexander Skavantzos
    Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1821-1824 [Conf]
  89. Farhad Fuad Islam, Keikichi Tamaru
    An Architecture for Intermediate Area-time Complexity Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1825-1828 [Conf]
  90. Stefan Wolter, Andreas Schubert, Holger Matz, Rainer Laur
    On the Comparison Between Architectures for the Implementation of Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1829-1832 [Conf]
  91. Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
    Methodology for the Design of Signed-digit DSP Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1833-1836 [Conf]
  92. Zhongde Wang, Graham A. Jullien, William C. Miller, June Wang
    New Concepts for the Design of Carry Lookahaead Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1837-1840 [Conf]
  93. Ishaq H. Unwala, Earl E. Swartzlander Jr.
    Superpipelined Adder Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1841-1844 [Conf]
  94. Karol Doerffer, Attila T. Téby, Oskar Anton, Dieter A. Mlynski
    KLaGen - A Generator of Static CMOS-cell Layout from Circuit Schematics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1845-1848 [Conf]
  95. Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang
    Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1849-1852 [Conf]
  96. Oskar Anton, Karol Doerffer, Dieter A. Mlynski
    Automatic Design of Transparent Standard Cells with TRANSCAD II. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1853-1856 [Conf]
  97. Charles Wiley, K. M. Lau, Stephen A. Szygenda
    m3D: A Multidimensional Dynamic Configurable Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1857-1860 [Conf]
  98. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
    Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1861-1864 [Conf]
  99. Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
    Minimum Density Interconneciton Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1865-1868 [Conf]
  100. Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
    A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1869-1872 [Conf]
  101. Yu Hen Hu, Chi-Yu Mao
    Solving Gate-Matrix Layout Problems by Simulated Evolution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1873-1876 [Conf]
  102. Hazem H. Ali, Mona E. Zaghloul
    VLSI Implementation of an Associative Memory Using Temporal Relations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1877-1880 [Conf]
  103. D. K. Harris-Dowsett, S. Summerfield
    Low Latency Architectures for Wave Digital Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1881-1884 [Conf]
  104. S. C. Chan, C. W. Kok, S. W. Chau
    Codebook Generation and Search Algorithm for Vector Quantization Using Arbitrary Hyperplanes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1885-1888 [Conf]
  105. Shaw-Min Lei
    Finite Word-length Effects on Arithmetic Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1889-1892 [Conf]
  106. Ghassan Y. Yacoub, Tarun Soni, Walter H. Ku
    A Compact Array Processor Based on Self-timed Simultaneous Bidirectional Signalling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1893-1896 [Conf]
  107. Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae
    Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1897-1900 [Conf]
  108. Laurent Letellier, Didier Juvin, Jean-Luc Basille, Jean Rebillat
    High Performance Graphics on a SIMD Linear Processor Array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1901-1904 [Conf]
  109. Hong-Yi Huang, Chung-Yu Wu
    Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1905-1908 [Conf]
  110. Clifford Sze-Tsan Choy, Wan-Chi Siu
    Generation of Chain-coded Contours and Contours Inclusion Relationship Under Multiprocessor Environment. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1909-1912 [Conf]
  111. C. J. Su, K. P. Lam
    Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1913-1916 [Conf]
  112. Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis
    CORDIC Based Pipeline Architecture for All-pass Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1917-1920 [Conf]
  113. Tsuyoshi Kawaguchi
    Static Allocation of a Task Tree onto a Linear Array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1921-1924 [Conf]
  114. Yi-Min Wang
    Reducing Message Logging Overhead for Log-based Recovery. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1925-1928 [Conf]
  115. Stephen P. S. Lam
    A New Approach to Reconfigure Faulty Systolic Array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1929-1932 [Conf]
  116. Moon Key Lee, Byeong Yoon Choi, Kwang Yub Lee, Seong Ho Lee
    Data-stationary Controller for 32-bit Application-specific RISC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1933-1936 [Conf]
  117. Young-Hyun Jun, Weon-Hwa Jeong, Jong-Hoon Park, Tae-Hoon Kim, Seong-Wook Kim, Jae-Sik Lee, Seong-Jin Jang, Chang-Man Khang, Hee-Gook Lee
    A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1937-1940 [Conf]
  118. J. David Narkiewicz, Wayne Burleson
    Rank-order Filtering Algorithms: A Comparison of VLSI Implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1941-1944 [Conf]
  119. Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
    A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1945-1948 [Conf]
  120. Fida H. Chishti, Anthony R. Clare, Moe Razaz
    Parallel Solution of Symmetric Banded Systems on Transputers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1949-1952 [Conf]
  121. Belle W. Y. Wei, Richard Tarver, Jong-Seop Kim, Kevin Ng
    A Single Chip Lempel-Ziv Data Compressor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1953-1955 [Conf]
  122. Naresh R. Shanbhag, Keshab K. Parhi
    A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1956-1958 [Conf]
  123. Kalavai J. Raghunath, Keshab K. Parhi
    High Speed RLS Using Scaled Tangent Rotations (STAR). [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1959-1962 [Conf]
  124. Robert W. Adams, Tom Kwan
    A Monolithic Asynchronous Sample-Rate Converter for Digital Audio. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1963-1966 [Conf]
  125. Mark W. Mao, B. Y. Chen, James B. Kuo
    A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1967-1970 [Conf]
  126. H. Khali, Jean-Louis Houle, Yvon Savaria
    A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1971-1974 [Conf]
  127. Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder
    Architecture and VLSI Design of a VLSI Neural Signal Processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1975-1978 [Conf]
  128. K. C. Lo, Alan Purvis
    Parallel Random Sampling with Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1979-1982 [Conf]
  129. Karol Doerffer, Oskar Anton, Dieter A. Mlynski
    Time Efficient Method for MOS Circuit Extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1983-1986 [Conf]
  130. Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya
    Test Generation for BiCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1987-1990 [Conf]
  131. Salil Raje, Majid Sarrafzadeh
    GEM: A Geometric Algorithm for Scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1991-1994 [Conf]
  132. Suresh Rai, Jerry L. Trahan, Thomas Smailus
    Processor Allocation in Faulty Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1995-1998 [Conf]
  133. K. J. Ray Liu, An-Yeu Wu
    A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1999-2002 [Conf]
  134. Chan S. Kim, Sang W. Song, Man Y. Kim, Young T. Han, Sang A. Kang, Bang W. Lee
    200 Mega Pixel Rate IDCT Processor for HDTVC Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2003-2006 [Conf]
  135. Kenneth J. Schultz, P. Glenn Gulak
    A Logic-enhanced Memory for Digital Data Recovery Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2007-2010 [Conf]
  136. Srini W. Seetharam, Gary J. Minden, Joseph B. Evans
    A Parallel SONET Scrambler/Descrambler Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2011-2014 [Conf]
  137. Laurent Lemaitre, Marek J. Patyra
    Fuzzy Logic Functions Synthesis - A CMOS Current Mirror Based Solution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2015-2018 [Conf]
  138. Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro
    A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2019-2022 [Conf]
  139. Mohamed Nekili, Yvon Savaria
    Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2023-2026 [Conf]
  140. James B. Kuo, H. P. Chen, H. J. Huang
    A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2027-2030 [Conf]
  141. D. Wagner, Subhash C. Kwatra, M. M. Jamali
    A Single Chip High Data Rate QPSK Demodulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2031-2034 [Conf]
  142. H. Kumar, Magdy A. Bayoumi, Akhilesh Tyagi, Nam Ling, R. Kalyan
    Parallel Implementation of a Cut and Paste Maze Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2035-2038 [Conf]
  143. Kuei-Ann Wen, Shihn-Cheng Chen, Jo-Tan Yao
    Single Processor Design for 2-D Wiener Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2039-2042 [Conf]
  144. Ray-I Chang, Pei-Yung Hsiao
    Arbitrarily Sized Cell Placement by Self-organizing Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2043-2046 [Conf]
  145. M. Kemal Unaltuna, Vijay Pitchumani
    Quadrisectioning Based Placement with a Normalized Mean Field Neural Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2047-2050 [Conf]
  146. M. Razaz
    A Fuzzy C-means Clustering Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2051-2054 [Conf]
  147. Achim G. Hoffmann
    A New Strategy for Library-independent Layout Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2055-2058 [Conf]
  148. Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
    Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2059-2062 [Conf]
  149. Bernd E. Freier
    Reducing the Physical Design Cycle by Means of Topological Placement with Hard Timing Restraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2063-2066 [Conf]
  150. Chen-Xiong Zhang
    Timing-, Heat- and Area-driven Placement Using Self-organizing Semantic Maps. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2067-2070 [Conf]
  151. E. I. Horvath
    A Parallel Force Direct Based VLSI Standard Cell Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2071-2074 [Conf]
  152. Christopher M. Wolff, Jung-hui Cheng
    Symbolic Precompilation of Piecewise-linear Behavioral Models for Efficient Simulation of Dual Time Scale Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2075-2078 [Conf]
  153. Subbarao Somanchi, Mark L. Manwaring
    Analog Synthesis from Behavioural Descriptions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2079-2082 [Conf]
  154. Jorge Chávez Orzáez, Miguel Angel Aguirre Echánove, Antonio Jesús Torralba Silgado
    Analog Design Optimization : A Case Study. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2083-2085 [Conf]
  155. Carlos A. Losada, David G. Haigh, Paul M. Radmore
    A Systematic Method for Nonlinear Analysis of a Class of FET Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2086-2089 [Conf]
  156. K. Wayne Current, Jim Parker, Wes Hardaker
    Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2090-2093 [Conf]
  157. Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi
    A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2094-2097 [Conf]
  158. Valentino Liberali, Enrico Malavasi, Davide Pandini
    Automatic Generation of Transistor Stacks for CMOS Analog Layout. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2098-2102 [Conf]
  159. N. S. Nagaraj
    A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2102-2105 [Conf]
  160. Kumar Venkat
    Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2106-2109 [Conf]
  161. Brian S. Cherkauer, Eby G. Friedman
    The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2110-2113 [Conf]
  162. Perng-Shyong Lin, Charles A. Zukowski
    Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2114-2117 [Conf]
  163. Huang Qiuting
    Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2118-2121 [Conf]
  164. José E. Schutt-Ainé, Kyung-soo Oh
    Modeling Interconnections with Nonlinear Discontinuities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2122-2124 [Conf]
  165. D. S. Gao, Dian Zhou
    Propagation Delay in RLC Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2125-2128 [Conf]
  166. Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong
    A Two-pole Circuit Model for VLSI High-speed Interconnection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2129-2132 [Conf]
  167. Richard M. M. Chen, Xing Dong Jia
    A Technique to Improve the Convergency Speed of Relaxation-based Simulations in Tightly Coupled Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2133-2136 [Conf]
  168. Hans Fleurkens, Pim H. W. Buurman
    Flexible Mixed-mode and Mixed-level Simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2137-2140 [Conf]
  169. Domenico Biey, Mario Biey, Maurizio Molinaro
    SCANSA: A Computer Program for the Statistical Analysis of Switched Capacitor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2141-2144 [Conf]
  170. Songxin Qi, Quanrang Yang
    An Improved Random Walk Approach for Yield Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2145-2147 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002