Conferences in DBLP
Jieyan Zhu , Mohamad Sawan , Karim Arabi An Offset Compensated CMOS Current-Feedback Operational-Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Eyad Abou-Allam , Ezz I. El-Masry Design of Wideband CMOS Current-Mode Operational Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Vasily G. Moshnyaga , Keikichi Tamaru A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Gerald E. Sobelman , Donovan L. Raatz Low-Power Multiplier Design Using Delayed Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Minkyu Song , Kunihiro Asada Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Yi Huang , Jinn-Shyan Wang , Yuan-Hua Chu , Tain-Shun Wu , Kuo-Hsing Cheng , Chung-Yu Wu Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Neves , Eby G. Friedman Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth J. Brauer , Sung-Mo Kang An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Jong Kug Seon , Kwang Sub Yoon A Precision Output Conductance Model for Analog CMOS Circuit Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Gerson A. S. Machado , Christian C. Enz , Matthias Bucher Estimating Key Parameters in the EKV MOST Model for Analogue Desgin and Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ana Isabela Araújo Cunha , S. M. Acosta , Márcio C. Schneider , Carlos Galup-Montoro An Explicit MOSFET Model for Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Qu , M. A. Styblinski An Adaptive Approach to Statistical Macromodeling of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Padmanabhan A Hyperstable Adaptive Line Enhancer for Frequency Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] P. C. Ching , K. F. Wan A Unified Approach to Split Structure Adaptive Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Ochi , Neil J. Bershad A New Frequency-Domain LMS Adaptive Filter with Reduced-Sized FFT's. [Citation Graph (0, 0)][DBLP ] Conf ] Pius Estermann , August Kaelin On the Comparison of Optimum Least-Squares and Computationally Efficient DFT-Based Adaptive Block Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Marcio G. Siqueira , Abeer A. Alwan , Paulo S. R. Diniz Finite Precision Analysis of the Fast QRD-RLS Lattice Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo A. B. da Silva , Demetrios G. Sampson , Mohammed Ghanbari Super High Definition Image Coding Using Successive Approximation Wavelet Vector Quantization. [Citation Graph (0, 0)][DBLP ] Conf ] Hsuan T. Chang , Chung J. Kuo An Improved Scheme for Fractal Image Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Juan Chao , Chen-Yi Lee A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Meina Xu , Anthony Kuh Unsupervised Learning Applied to Image Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Hung Yuen , Kam-Chi Li , Lajos Hanzo Efficient Variable Rate Vector Quantization Using Quadtree Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar Moreira-Tamayo , José Pineda de Gyvez Time Domain Analog Wavelet Transform in Real-Time. [Citation Graph (0, 0)][DBLP ] Conf ] Ramanatham Gudipati , Wai-Kai Chen Explicit Formulas for the Design of Broadband Matching Bandpass Equalizers with Chebyshev Response. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine Dehollain , Jacques Neirynck Broadband Matching of an RLC Load by Optimal Chebyshev Gain Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Artice M. Davis K infinity Generalized Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Mao-Da Tong , Wai-Kai Chen Application of Return Difference Matrix to Stability Analysis for Multivariable Feedback Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Hasler , Chris Diorio , Bradley A. Minch , Carver Mead Single Transistor Learning Synapse with Long Term Storage. [Citation Graph (0, 0)][DBLP ] Conf ] Bing J. Sheu , Theodore W. Berger , Tony H. Wu , Richard H. Tsai VLSI Neural Network Implementation of a Hippocampal Model. [Citation Graph (0, 0)][DBLP ] Conf ] Yngvar Berg , Jon-Erik Ruth , Tor Sverre Lande Scalable Mean Rate Signal Encoding Analog Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Teresa Serrano-Gotarredona , Bernabé Linares-Barranco Experimental Results of an Analog Current-Mode ART1 Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Feng Lan , Chung-Yu Wu CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory. [Citation Graph (0, 0)][DBLP ] Conf ] D. T. Lee , Chin-Fang Shen , Cheng-Liang Ding On Steiner Tree Problem with 45 Degree Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Christie , Mark D. Loose , Alexander V. Chernoguzov Simulated Isobaric Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Ping Chen , D. F. Wong A Graph Theoretic Approach to Feed-Through Pin Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Myong H. Cynn , Sung-Mo Kang Incremental Node Extraction Algorithms for Incremental Layout System. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Ti Huang , David Overhauser A Novel Graph Algorithm for Circuit Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. Bostel Training Radial Basis Function Networks with Perturbation Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Cesare Furlanello , Diego Giuliani , Edmondo Trentin , Daniele Falavigna Application of Generalized Radial Basis Functions In Speaker Normalization and Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Shaohua Tan , Jianbin Hao , Joos Vandewalle A New Learning Algorithm for RBF Neural Networks with Applications to Nonlinear System Identification. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bruzzo , Francesco Camastra , Anna Maria Colla Estimation of Unmeasurable Variables in a Dynamical System by Resource Allocating Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamad T. Musavi , D. R. Coughlin , M. Qiao Prediction of Wood Pulp kappa# with Radial Basis Function Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Frode Larsen , Mohammed Ismail The Design of High Performance Low Cost BiCMOS Op-amps in a Predominantly CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] W. Timothy Holman , J. Alvin Connelly A Pseudo-BiCMOS High Gain-Bandwidth Low Noise Operational Amplifier Using a Darlington Input Stage. [Citation Graph (0, 0)][DBLP ] Conf ] Klaas-Jan de Langen , Jeroen Fonderie , Johan H. Huijsing Limiting Circuits for Rail-To-Rail Output Stages of Low-Voltage Bipolar Operational Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Helfenstein , Qiuting Huang , George S. Moschytz 90Db, 90MHz, 30m W OTA with the Gain-Enhancement Implemented by One and Two Stage Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Simon , Johann Hofner , Josef A. Nossek Retiming of Circuits Containing Multiplexers. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Lejmi , Bozena Kaminska , Bechir Ayari Retiming for BIST-Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shihming Liu , Massoud Pedram , Alvin M. Despain PLATO P: PLA Timing Optimization by Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Tolga Soyata , Eby G. Friedman , James H. Mulligan Jr. Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Juraj Valsa , Jiri Vlach SWANN - A Program for Analysis of Switched Analog Nonlinear Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Patrik Larsson Fast and Accurate Event Driven Simulation of Partly Analog Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Walter E. Thain , J. Alvin Connelly Simulating Phase Noise in Phase-Locked Loops with a Circuit Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Bishop , André Ivanov Fault Simulation of an OTA Biquadratic Filter. [Citation Graph (0, 0)][DBLP ] Conf ] M. Tahernezhadi , S. C. Manapragada , J. Liu Subband Acoustic Echo Cancellation Using a Thin Lattice Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffrey A. Williamson Implementations of Adaptive IIR Filters with Lowest Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Shotaro Nishimura , Koji Matsutani Steady-Stae Analysis of a Second-Order Adaptive IIR Notch Filter Using the Sign Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo S. R. Diniz , Juan E. Cousseau A Family of Consistent Steiglitz-McBride Algorithms for IIR Adaptive Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Wilson C. Chung , Faouzi Kossentini , Mark J. T. Smith A Subband Coding Method for HDTV. [Citation Graph (0, 0)][DBLP ] Conf ] Faouzi Kossentini , Wilson C. Chung , Mark J. T. Smith Subband Coding of Color Images Using Multiplierless Encoders and Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Peter N. Heller , Vasily Strela , Gilbert Strang , Pankaj Topiwala , Christopher Heil , L. S. Hills Multiwavelet Filter Banks for Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Coen , Daniel De Zutter Elimination of Mutual Couplings in Discrete Element Networks Arising from the Modeling of High Speed Digital Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] G. Guida , G. Miano , L. Verolino Nonlinear Dynamics in a Distributed Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Lennart Harnefors , Kåre Mossberg Sampling of Quadrature-Phase Quantities. [Citation Graph (0, 0)][DBLP ] Conf ] L. Corti , G. Miano , L. Verolino Analysis of Transmission Lines Nonlinear Loaded Using Galerkin Method. [Citation Graph (0, 0)][DBLP ] Conf ] Rafiqul Islam , Makoto Hiroshige , Yoshikazu Miyanaga , Koji Tochinai Phoneme Recognition System Based on a Modified TDNN Using Self-Organizing Clustering Network. [Citation Graph (0, 0)][DBLP ] Conf ] William Robertson , Selçuk Sen , William J. Phillips The Investigation of Using Limited Precision on a TDNN for Consonant Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Majid M. Altowairjri , Magdy A. Bayoumi A New Thinning Algorithm for Arabic Character Using Self-Organizing Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Jesús Torralba Silgado , Jorge Chávez Orzáez , Leopoldo García Franquelo Fault Detection and Classification of Analog Circuits by Means of Fuzzy Logic-Based Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Fa Mao , Omar Wing , Fung-Yuel Chang Time-Domain Model of Transmission Lines with Arbitrary Initial Potential and Current Distributions for Transient Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Nishath K. Verghese , David J. Allstot A Macromodel Compaction Scheme for the Fast Stimulation of Large Linear Mesh Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] S. Cyrusian Time Domain Based Modeling of Lossy Coupled Transmission Lines by Approximation of Transfer Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Scott D. Huss A Mathematical and Lumped-Element Model for Multiple Cascaded Lossy Transmission Lines with Arbitrary Impedances and Discontinuities. [Citation Graph (0, 0)][DBLP ] Conf ] Yuming Cao , Gabor C. Temes CMOS Circuits for On-Chip Capacitance Ratio Testing or Sensor Readout. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund Pierzchala , Rolf Schaumann , Paul Van Halen , Stanislaw Szczepanski , Marek A. Perkowski Highly Linear VHF Current-Mode Miller Integrator with 900 dB DC Gain. [Citation Graph (0, 0)][DBLP ] Conf ] G. H. M. Joordens , J. A. Hegt , Domine Leenaerts A High Performance Low Voltage Switched-Current Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] T. Maurel , R. Bouchakour , Christophe Lallement One-Dimensional Model of the Power Bipolar Transistor with Thermoelectrical Interactions for Circuit Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jay L. Brown High Sensitivity Magnetic Field Sensor Using GMR Materials with Integrated Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] José Silva-Martínez , Jorge Salcedo-Suñer A CMOS Preamplifier for Electret Microphones. [Citation Graph (0, 0)][DBLP ] Conf ] T. L. Lim , David G. Haigh , D. R. Webster On the Design of Active GaAs Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Soo-Chang Pei , Min-Hung Yeh Time Frequency Split Zak Transform for Finite Gabor Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Draidi , L. M. Khadra , M. A. Khasawneh Generalized Cone-Shaped Kernels for Time-Frequency Distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Hung Leung , Fung-Yuel Chang Transient Analysis Via Fast Wavelet-Based Convolution. [Citation Graph (0, 0)][DBLP ] Conf ] X. Q. Gao , H. Zhang , Z. Y. He Subband Model and Implementation of 0-QAM System. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Pak-Kong Lun , Tai-Chiu Hsung , Wan-Chi Siu On the Convolution Property of a New Discrete Radon Transform and its Efficient Inversion Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Dinu Coltuc , Ioannis Pitas Jordan Decomposition Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Jaakko Astola , Pauli Kuosmanen , David Akopian , David Z. Gevorkian Fibonacci P-Code Method for Generalized Stack Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Ram G. Shenoy Model-Matching Design of Sample-Rate Changers: Asymptotic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Krajnik On Time-Domain Deconvolution and the Computation of the Cepstrum. [Citation Graph (0, 0)][DBLP ] Conf ] Geetani Edirisooriya , Samantha Edirisooriya Scan Chain Fault Diagnosis with Fault Dictionaries. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiro Nakaoa , Shin'ichi Wakabayashi , Tetsushi Koide , Noriyoshi Yoshida A Verification Algorithm for Logic Circuits with Internal Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Buonanno , Fabio Salice , Donatella Sciuto Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Boubezari , Bozena Kaminska Mixed Deterministic and Pseudorandom Test Vector Generator Based on Cellular Automata Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Juhani Vehvilainen , Jari Nurmi A Processor Core for 32 kbit/s G.726 ADPCM Codecs. [Citation Graph (0, 0)][DBLP ] Conf ] Sonali Bagchi , Sanjit K. Mitra An Efficient Algorithm for DTMF Decoding Using the Subband NDFT. [Citation Graph (0, 0)][DBLP ] Conf ] R. Perry , David R. Bull , A. Nix Algorithms for Flexible Equalisation in Wireless Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiaki Shishikui A Study on Introduction of PSD Model for Field Merged Signal and Its Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Sinclair , Mohamad T. Musavi , M. Qiao Radial Basis Function Neural Network as Predictive Process Control Model. [Citation Graph (0, 0)][DBLP ] Conf ] Wahid Ahmed , Donald M. Hummels , Mohamad T. Musavi Application of Fast Orthogonal Search for the Design of RBFNN. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Laine , Chun-Ming Chang De-Noising via Wavelet Transforms Using Steerable Filters. [Citation Graph (0, 0)][DBLP ] Conf ] A. Caiti , T. Parsini Approximation of Inverse Maps through RBF Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yu Wu , Shuo-Yuan Hsiao , Ron-Yi Liu A 3-V 1-GHz Low-Noise Bandpass Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jamal Deen , Duljit S. Malhi , Zhixin Yan , Robert A. Hadaway A New Mixer Circuit Using a Gate-Controlled LPNP BJT. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin J. Blalock , Phillip E. Allen A Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Fan You , Sherif H. K. Embabi , Edgar Sánchez-Sinencio , A. Ganesan A Design Scheme to Stabilize the Active Gain Enhancement Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Caiulo , Piero Malcovati , C. Bona , Franco Maloberti Novel Circuit Solutions for Rail-to-Rail CMOS Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Hao-Yung Lo , Hsiu-Feng Lin , Kuen-Shiuh Yang A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoyun Wang , Earl E. Swartzlander Jr. Merged CORDIC Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] I. Orginos , Vassilis Paliouras , Thanos Stouraitis A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Hiasat , Hoda S. Abdel-Aty-Zohdy High-Speed Division Algorithm for Residue Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian T. J. Fenn , Mohammed Benaissa , David Taylor Bit-Serial Dual Basis Systolic Multipliers for GF 2m . [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Shung-Chih Chen Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Wang Jiang Chau , Edward P. Stabler Collective Test Generation and Test Set Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Buonanno , Fabrizio Ferrandi , Donatella Sciuto Data Path Testability Analysis Based on BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Franco Fummi , R. Gemelli , Fabio Salice A BDD Based Algorithm for Detecting Difficult Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed A. El-Gamal , Abdel-Karim S. O. Hassan , Hany L. Abdel-Malek A New Approach for the Selection of Test Points for Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce W. Bomar , L. Montgomery Smith , Roy D. Joseph Roundoff Noise Analysis of State-Space Digital Filters Implemented on Floating-Point Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Jy Shyu , Yuan-Chih Lin Design of Finite-Wordlength IIR Digital Filters in the Time/Spatial Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Li , Guoan Bi Simultaneous Minimization of Pole and Zero Sensitivity in Digital Filter Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal Premaratne , E. C. Kulasekere , Peter H. Bauer , L. J. Leclerc An Exhaustive Search Algorithm for Checking Limit Cycle Behavior of Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Hinamoto , Hirofumi Yamada , Yoshitaka Zempo Weighted Sensitivity Minimization Synthesis of 2-D Filter Structures Using the Fornasini-Marchesini Second Model. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Luchetta , Stefano Manetti , Maria Cristina Piccirilli , Alberto Reatti Frequency-Domain Analysis of DC/DC Converters Using a Symbolic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Marian K. Kazimierczuk , Robert Cravens II Input Impedance of Closed-Loop PWM Buck-Boost DC-DC Coinverter for CCM. [Citation Graph (0, 0)][DBLP ] Conf ] Y. S. Lee , K. W. Siu , Xuan-Zhong Liu Optimizing the Design of Switch-Mode Power Supplies with Battery Back-Up and Power Factor Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Giral , Luis Martínez , Javier Hernanz , Javier Calvente , Francesc Guinjoan , Alberto Poveda , R. Leyva Compensating Networks for Sliding-Mode Control. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon W. Roberts Calculating Distortion Levels in Sampled-Data Circuits Using SPICE. [Citation Graph (0, 0)][DBLP ] Conf ] D. G. Nairn , A. Biman Optimizing the Performance of Switched Current Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John B. Hughes , Kenneth W. Moulding Switched-Current Cells for Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Nianxiong Tan On Switched-Current Delta-Sigma A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Marian Pierzchala , Benedykt Rodanski Obtaining Symbolic Network Functions of Large Circuits - An Algebraic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Erich Wehrhahn Symbolic Analysis of Large Linear Circuits with the Bilinear-Splitting Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Jaw Hsu , Carl Sechen Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Qicheng Yu , Carl Sechen Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Wang , Lex A. Akers Hardware Implementation of Habituation. [Citation Graph (0, 0)][DBLP ] Conf ] Richard C. Meitzler , Kim Strohbehn , Andreas G. Andreou A Silicon Retina for 2-D Position and 2-D Motion Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Bing J. Sheu Constructing Intelligent Microsystems with Modular VLSI Networks Design. [Citation Graph (0, 0)][DBLP ] Conf ] C. K. Tse , M. H. L. Chow A New Clock-Feedthrough Cancellation Method for Second Generation Switched-Current Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] ThartFah Voo , Chris Toumazou A Novel High Speed Current Mirror Compensation Technique and Application. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Punzenberger , Christian C. Enz Low-Voltage Companding Current-Mode Integrators. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Azadet , Alex G. Dickinson , David A. Inglis A Mismatch-Free CMOS Dynamic Voltage Comparator. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele A Self-Test Approach Using Accumulators as Test Pattern Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Lidén , Peter Dahlgren Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Yoon-Hwa Choi , Chul Kim , Edward Jung Configuring Multiple Boundary Scan Chains for Board Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Bechir Ayari , Bozena Kaminska BDD-FTEST: Fast, Backtrack-Free Test Generator Based on Binary Decision Diagram Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Donatella Sciuto An Output/State Encoding for Self-Checking Finite State Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Spence , Ravinder S. Bhogal , Lisa Tweedie , Hua Su Responsive Visualisation - A Tool for Analog Designers. [Citation Graph (0, 0)][DBLP ] Conf ] M. Sengupta , M. A. Styblinski An Efficient Jacobian Updating Technique for Analog Circuit Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] R. Rodriguez-Macias , Francisco V. Fernández , Ángel Rodríguez-Vázquez , José L. Huertas A Tool for Fast Mismatch Analysis of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Shen , Richard M. M. Chen Application of Genetic Algorithm for Response Surface Modeling in Optimal Statistical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chrissavgi Dre , Anna Tatsaki , Thanos Stouraitis , Constantinos E. Goutis Alternative Architectures for the 2-D DCT Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Riccardo Bernardini , Guido M. Cortelazzo , Gian Antonio Mian A MD FFT Algorithm for Symmetric Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Susanto Rahardja Fast Transforms for Orthogonal Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Chip-Hong Chang Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Salvatore Baglio , Rosario Cristaudo , Luigi Fortuna , Donato Tagliavia A Mixed Electrical-Functional Model Strategy to Investigate the Nonlinear Behaviors of an Experimental Flyback Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Angelo Brambilla , Dario D'Amore , Mauro Santomauro A New Technique for Transient Analysis of Periodically Switched Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] D. Shmilovitz , S. Singer Current Averaging Networks Based on Transmission Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Emil M. Petriu , Kenzo Watanabe , Tet H. Yeap , Satomi Ogawa Neural Network Architecture Using Random-Pulse Data Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Costa , Davide Palmisano , Eros Pasero NESP: An Analog Neural Signal Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Mange , Serge Durand , Eduardo Sanchez , André Stauffer , Gianluca Tempesti , Pierre Marchal , Christian Piguet A New Paradigm for Developing Digital Systems Based on a Multi-Cellular Organization. [Citation Graph (0, 0)][DBLP ] Conf ] Cesare Alippi , Raffaele Petracca , Vincenzo Piuri Off-Line Performance Maximisation in Feed-Forward Neural Networks by Applying Virtual Neurons and Covariance Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Yuang-Ming Hsu , Vincenzo Piuri , Earl E. Swartzlander Jr. Fault-Tolerant Neural Architectures: The Use of Rotated Operands. [Citation Graph (0, 0)][DBLP ] Conf ] Georges G. E. Gielen , Geert Debyser , Piet Wambacq , Koen Swings , Willy M. C. Sansen Use of Symbolic Analysis in Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] A. Liberatore , Antonio Luchetta , Stefano Manetti , Maria Cristina Piccirilli A New Symbolic Program of Package for the Interactive Design of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Helena Fino , José E. da Franca , Adolfo Steiger-Garção Automatic Symbolic Characterization of SC Multirate Circuits with Finite Grain Operational Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] A. Konczykowska , Wlodzimierz M. Zuberek Function Evaluation in Symbolic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Styblinski , Ming Qu Comparison of Symbolic Approximation and Macromodelling Techniques for Statistical Design of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Erik J. Hogenbirk , Huibert-Jan Verhoeven , Johan H. Huijsing An Integrated Smart Sensor for Flow and Temperature with I2C Bus Interface: FTS2. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad Baghai Dowlatabadi , J. Alvin Connelly A New Offset Cancellation Technique for CMOS Differential Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Diorio , Sunit Mahajan , Paul E. Hasler , Bradley A. Minch , Carver Mead A High-Resolution Non-Volatile Analog Memory Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Delgado-Restituto , Rafael López de Ahumada , Ángel Rodríguez-Vázquez Secure Communication Through Switched-Current Chaotic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] A. Häberli , Piero Malcovati , D. Jäggi , Henry Baltes , Franco Maloberti High Dynamic Range Interface System for a Micromachined Integrated AC-Power Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] J. Francisco Duque-Carrillo , Guido Torelli , R. Pérez-Aloe , J. M. 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