Conferences in DBLP
Walt T. Bax , Tom A. D. Riley , Calvin Plett , Miles A. Copeland A Sigma-Delta Frequency Discriminator Based Synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Galton A Practical Second-Order Delta-Digma Frequency-to-Digital Converter. [Citation Graph (0, 0)][DBLP ] Conf ] P. Ju , K. Suyama , P. Ferguson , W. Lee A Highly Linear Switched-Capacitor DAC for Multi-Bit Sigma-Delta D/A Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Rex T. Baird , Terri S. Fiez Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. [Citation Graph (0, 0)][DBLP ] Conf ] Mervyn H. Adams , Chris Toumazou A Novel Architecture for Reducing the Sensitivity of Multibit Sigma-Delta ADCs To DAC Nonlinearity. [Citation Graph (0, 0)][DBLP ] Conf ] Anura P. Jayasumana , Yashwant K. Malaiya , Sankaran M. Menon A Novel High-Speed BiCMOS Domino Logic Family. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yu Wu , Jr-Houng Lu , Kuo-Hsing Cheng A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Hidalgo-López , J. C. Tejero , J. Fernández , A. Gago New Types of Digital Comparators. [Citation Graph (0, 0)][DBLP ] Conf ] R. X. Gu , Mohamed I. Elmasry Power Dissipation in Deep Submicron CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan A. Kühn , Michael B. Kleiner , Roland Thewes , Werner Weber Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Capacitive Coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelhakim Safir , Baher Haroun , Krishnaiyan Thulasiraman Floorplanning with Datapath Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Yuan Chao , D. F. Wong Floorplanning for Low Power Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Morteza Saheb Zamani , Graham R. Hellestrand A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Piyush K. Sancheti , Sachin S. Sapatnekar Layout Optimization Using Arbitrarily High Degree Posynomial Models. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Liang Lin , Majid Sarrafzadeh A Linear Arrangement Problem with Applications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Tawfik , Panajotis Agathoklis , Fayez El Guibaly New IIR Digital Filter Realizations Using Residue-Feedback. [Citation Graph (0, 0)][DBLP ] Conf ] Svante Signell , Todor Kouyoumdjiev , Kåre Mossberg , Lennart Harnefors Design of Bilinear Digital Ladder Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Svante Signell , Lennart Harnefors Analysis of Bilinear Digital Ladder Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Kasyapa Balemarthy , Steven C. Bass General, Linear Boundary Conditions in MD Wave Digital Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Gyun Chung , Keshab K. Parhi Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain. [Citation Graph (0, 0)][DBLP ] Conf ] XuDuan Lin , KyungHi Chang , Jaeseok Kim Optimal PN Sequences Design for Quasi-Synchronous CDMA Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] C. A. Carty , M. M. Jamali , A. G. Eldin , Subhash C. Kwatra , R. E. Jones A High Speed 800 Channel Digital Interpolator Network. [Citation Graph (0, 0)][DBLP ] Conf ] S. Subramanian , Dale J. Shpak , Andreas Antoniou Performance of a Quasi-Newton Adaptive Filtering Algorithm for a CDMA Indoor Wireless System. [Citation Graph (0, 0)][DBLP ] Conf ] Nabil Abd Rabou , Hiroaki Ikeda , Hirofumi Yoshida Wideband Optical Fiber Signal Transmission System of 300MHz Bandwidth Using LED. [Citation Graph (0, 0)][DBLP ] Conf ] Norman M. Filiol , Calvin Plett , Tom A. D. Riley , Miles A. Copeland Bit-Error Rate Measurements for A High Frequency Interpolated Frequency-Hopping Spread-Spectrum System. [Citation Graph (0, 0)][DBLP ] Conf ] Arturo Sarmiento-Reyes A Novel Method to Predict Both, the Upper Bound on the Number and the Stability of DC Operating Points of Transistor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael M. Green A Method for Identifying Combinations of Transistors that can be Replaced with a Single Transistor when Applying the Nielsen-Willson Theorem. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Fox Design-Oriented Analysis of CD Operating-Point Instability. [Citation Graph (0, 0)][DBLP ] Conf ] S. W. Ng , Y. S. Lee , C. K. Tse , S. C. Wong Stability of a Circuit with Parasitic Capacitances. [Citation Graph (0, 0)][DBLP ] Conf ] Michael M. Green , Robert C. Melville Sufficient Conditions for Finding Multiple Operating Points for CD Circuits Using Continuation Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Syozo Yasui , Aleksander Malinowski , Jacek M. Zurada Convergence Suppression and Divergence Facilitation: New Approach to Prune Hidden Layer and Weights of Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Seijas , José L. Sanz-González Basic-Evolutive Algorithms for Neural Networks Architecture Configuration and Training. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksander Malinowski , Tomasz J. Cholewo , Jacek M. Zurada Capabilities and Limitations of Feedforward Neural Networks with Multilevel Neurons. [Citation Graph (0, 0)][DBLP ] Conf ] Ruey-Wen Liu , Yih-Fang Huang , Xie-Ting Ling A Novel Approach to the Convergence of Unsupervised Learning Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford Sze-Tsan Choy , Pui-Kin Ser , Wan-Chi Siu Peak Detection in Hough Transform Via Self-Organizing Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Belkhayat , Roger E. Cooley , Eyad H. Abed Stability and Dynamics of Power Systems with Regulated Converters. [Citation Graph (0, 0)][DBLP ] Conf ] X. Jiang , Heinz Schättler , John Zaborszky , Vaithianathan Venkatasubramanian Hard Limit Induced Oscillations. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Pai , Mark Laufenberg On the Computation of Hetero Clinic Orbits in Dynamical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiya Mashima , Toshimasa Watanabe Approximation Algorithms for the k-Edge-Connectivity Augmentation Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Tamura , Ryohei Sato , Masakazu Sengoku , Shoji Shinoda , Takeo Abe The Structure of Networks Realized from Terminal Capacity Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo E. Téllez , Majid Sarrafzadeh On Rectilinear Distance-Preserving Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Wang , Wai-Kai Chen Floorplan Area Optimization Using Network Analogous Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Omid Shoaei , W. Martin Snelgrove A Multi-Feedback Design for LC Bandpass Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Mats Erling Høvin , Alf Olsen , Tor Sverre Lande , Chris Toumazou Delta-Sigma Converters Using Frequency-Modulated Intermediate Values. [Citation Graph (0, 0)][DBLP ] Conf ] Huibert-Jan Verhoeven , Johan H. Huijsing Design of Thermal Sigma-Delta Modulators for Smart Thermal Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Mittal , David J. Allstot Low-Power High-Speed Continuous-Time Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet Soyuer , Herschel A. Ainspan , John F. Ewen A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Fuminori Kobayashi , Masayuki Haratsu A Digital PLL with Finite Impulse Responses. [Citation Graph (0, 0)][DBLP ] Conf ] Patrik Larsson A Wide-Range Progammable High-Speed CMOS Frequency Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Jiin-Chuan Wu , Hun-Hsien Chang A 550MHz 9.3mW CMOS Frequency Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Patrick H. Madden Performance Driven Routing with Mulitiple Sources. [Citation Graph (0, 0)][DBLP ] Conf ] Shashidhar Thakur , Kai-Yuan Chao , D. F. Wong An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Miyoshi , Shin'ichi Wakabayashi , Tetsushi Koide , Noriyoshi Yoshida An MCM Routing Algorithm Considering Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Cheng-Kok Koh Minimum-Cost Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Anissa Zergaïnoh , Pierre Duhamel , Jean Pierre Vidal DSP Implememntation of Fast FIR Filtering Algorithms Using Short FFT's. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Liang Chen , Kei-Yong Khoo , Alan N. Willson Jr. An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhiko Yagyu , Toshiyuki Yoshida , Akinori Nishihara , Nobuo Fujii Design of FIR Digital Filters with Minimum Weight Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Darren N. Pearson , Keshab K. Parhi Low-Power FIR Digital Filter Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Tak Po Chan , Bing Zeng , Ming L. Liou Visual Pattern BTC with Two Principle Colors for Color Images. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Maccato , Rui J. P. de Figueiredo The Image and Associated Orientation Signatures. [Citation Graph (0, 0)][DBLP ] Conf ] W. K. Lam , C. K. Li Classification of Rotated and Scaled Textures by Local Linear Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Halûk Aydinoglu , Monson H. Hayes Stereo Image Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Gilli A Spectral Approach for Studying Spatio-Temporal Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] L. M. Khadra , T. J. Maayah , M. Vinson , H. Dichhauss Chaos Detection in Time Series: A Statistical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kunihiko Mitsubori , Toshimichi Saito A Hysteresis Hyperchaos Generator Family. [Citation Graph (0, 0)][DBLP ] Conf ] Hisa-Aki Tanaka , Kazuo Horiuchi , Shin'ichi Oishi Chaos from Orbit-Flip Homoclinic Orbits Generated in Real Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Scholles , Bedrich J. Hosticka , Markus Schwarz Real-Time Application of Biology-Inspired Neural Networks Using and Emulator with Dedicated Communication Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Ammar B. A. Gharbi , Fathi M. A. Salam Implementation and Test Results of a Chip for the Separation of Mixed Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Jaime Ramírez-Angulo A BiCMOS Universal Membership Function Circuit with Fully Independant, Adjustable Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Colodro Ruiz , Antonio Jesús Torralba Silgado , Leopoldo García Franquelo A Circuit for Learning in Fuzzy Logic-Based Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Chi Chu , Hsiao-Dong Chiang , James S. Thorp An Investigation of Invariant Properties of Unstable Equilibrium Points on the Stability Boundary for Simple Power System Models. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Rajaraman , Ian Dobson Damping and Incremental Energy in Thyristor Switching Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yu Wu , Heng-Shou Hsu The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters. [Citation Graph (0, 0)][DBLP ] Conf ] R. F. Wolffenbuttel , G. de Graaf , E. Engen Bipolar Circuits for Readout of an Integrated Silicon Color Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Bruun Bandwidth Limitations in Current Mode and Volage Mode Integrated Feedback Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] C. S. Choy , C. F. Chan , M. H. Ku A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. [Citation Graph (0, 0)][DBLP ] Conf ] D. Perry , Gordon W. Roberts Log-Domain Filters Based on LC Ladder Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Di Cataldo , Giovanni Palmisano , Gaetano Palumbo A CMOS CCII+. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Wang , Ramesh Harjani Dynamic Amplifiers: Settling, Slewing and Power Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Shah , Chris Toumazou A New BiCMOS Technique for Very Fast Discrete-Time Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Manduchi 2-D IFIR Structures Using Generalized Factorable Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Pavel Zahradnik , Rolf Unbehauen Frequency Shift of Two-Dimensional Real Coefficient Zero Phase Fir Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Pokala , Arnab K. Shaw Optimal Spatial-Domain Design Analogues in Optimal System Identification. [Citation Graph (0, 0)][DBLP ] Conf ] H. Safiri , Majid Ahmadi , V. Ramachandran Design of 2-Dimensional Digital Filters Using 2-D All-Pass Building Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Rajamohana Hegde , B. A. Shenoi Design of 2-D IIR Filters Using a New Digital Spectral Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Hinamoto , Shuji Karino , Naoki Kuroda Error Spectrum Shaping in 2-D Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Haiyun Luo , Songwu Lu , Andreas Antoniou New Algorithm for Structurally Balanced Model Reduction of 2-D Discrete Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Haiyun Luo , Songwu Lu , Andreas Antoniou A Weighted Balanced Realization of 2-D Discrete Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vesa Välimäki A New Filter Implementation Strategy for Lagrange Interpolation. [Citation Graph (0, 0)][DBLP ] Conf ] Miki Haseyama , Tohru Hirohku , Hideo Kitajima A Realization Method of an ARMAX Lattice Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Y. Tetelbaum Path Search for Complicated Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten F. Ball , Andreas Just , Dieter A. Mlynski A Fuzzy Mean Field Approach for Partitioning and Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard M. Riess , Gisela G. Ettelt Speed: Fast and Efficient Timing Driven Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao Quan Li , Marwan A. Jabri Neural Network Based Estimation of VLSI Building Block Dimensions from Schematic. [Citation Graph (0, 0)][DBLP ] Conf ] M. Kemal Unaltuna , Vijay Pitchumani ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ian M. Bell , Kevin R. Eckersall , Stephen J. Spinks , Gaynor E. Taylor Fault Orientated Test and Fault Simulation of Mixed Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Jou Tang , Bin-Da Liu , Kuen-Jong Lee An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Wolter , Holger Matz , Andreas Schubert , Rainer Laur On the VLSI Implementation of the International Data Encryption Algorithm IDEA. [Citation Graph (0, 0)][DBLP ] Conf ] William A. Chren Jr. One-Hot Residue Coding for High-Speed Non-Uniform Pseudo-Random Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Gary C. Moyer , Mark Clements , Wentai Liu , Toby Schaffer , Ralph K. Cavin III High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen-Jong Lee , Sheng-Yih Jeng , Tian-Pao Lee A New Architecture for Analog Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Kramer , Rahul Sarpeshkar , Christof Koch An Analog VLSI Velocity Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] M. Salerno , F. Sargeni , V. Bonaiuto DPCNN: A Modular Chip for Large CNN Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Chua-Chin Wang , Jeng-Ming Wu Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Wang Baoyun , Luxi Yang , Hongtao Lu , Zhenya He On the Capacity of Intraconnected Bidirectional Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihiko Horio , Ken Suyama Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Doggett , Graham R. Hellestrand A Hardware Architecture for Video Rate Shading of Volume Data. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Fu , Keshab K. Parhi Generalized Multiplication Free Arithmetic Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Hugh Q. Cao , Weiping Li A New Multilevel Codebook Searching Algorithm for Vector Quantization. [Citation Graph (0, 0)][DBLP ] Conf ] A. Nabout , Bing Su , H. A. Nour Eldin A Novel Closed Contour Extractor, Principle and Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Yui-Lam Chan , Wan-Chi Siu Fast Interframe Transfrom Coding Based on Characteristics of Transform Coefficients and Frame Difference. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Provine , Leonard T. Bruton Lip Synchronization in 3-D Model Based Coding for Video-Conferencing. [Citation Graph (0, 0)][DBLP ] Conf ] Touradj Ebrahimi , Homer H. Chen , Barry G. Haskell A Region Based Motion Compensated Video Codec for Very Low Bitrate Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Il Chang , Young-kwon Cho , SouGuil Ann A New Wavelet Tranform-Based CELP Coder with Band Selection and Selective VQ. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Hung-Kei Chow , Ming L. Liou Simple Cell Admission Control and Buffer Management Scheme for Mulitclass Video-On-Demand Service. [Citation Graph (0, 0)][DBLP ] Conf ] R. K. Bertschmann , N. R. Bartley , Leonard T. Bruton A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Raffaele Parisi , Elio D. Di Claudio , Gianni Orlandi Total Least Squares Approach for Fast Learning in Multilayer Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Wu Meng , Feng Guangzeng A Multi-Solution Learning Algorithm for Fuzzy Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshikazu Miyanaga , Honglan Jin , Rafiqul Islam , Koji Tochinai A Self-Organized Network with a Supervised Training. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Wang , Ce Zhu , Chenwu Wu , Zhenya He Neural Network Approaches to fast and Low Rate Vector Quantization. [Citation Graph (0, 0)][DBLP ] Conf ] Aijit Dingankar , Irwin W. Sandberg On Error Bounds for Neural Network Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Kamio , Hiroshi Ninomiya , Hideki Asai Convergence of Hopfield Neural Network for Orthogonal Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Tzuu-Hseng S. Li , Chyi-Cherng Lai Lyapunov Function Based Fuzzy State Estimator. [Citation Graph (0, 0)][DBLP ] Conf ] Mark P. Joy , Vedat Tavsanoglu Circulant Matrices and the Stability of Ring CNNs. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Arena , Luigi Fortuna , Giovanni Muscato , Maria Gabriella Xibilia Fast Learning by Weight Estimation in Complex Valued MLPs. [Citation Graph (0, 0)][DBLP ] Conf ] Morikazu Nakamura , Kenji Onaga , Seiki Kyan , Manuel Silva A Genetic Algorithm for Sex-Fair Stable Marriage Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Nakagawa , Dong-Ik Lee , Sadatoshi Kumagai , Shinzo Kodama Equivalent Net Abstraction and Firing Sequence Preservation. [Citation Graph (0, 0)][DBLP ] Conf ] Tadao Murata , Jaegeol Yim Petri-Net Methods for Reasoning in Real-Time Control Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Togashi , Nobuyuki Usui , Kukhwan Song , Norio Shiratori A Derivation of System Specifications Based on a Partial Logical Petri Net. [Citation Graph (0, 0)][DBLP ] Conf ] João Goes , João C. Vital , José E. Franca Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Guilherme , José E. Franca New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zheng Tang , Yuichi Shirata , Okihiko Ishizuka , Koichi Tanno A Self-Calibrating A/D Converter Using T-Model Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Cheng Chen , Chung-Yu Wu , Jyh-Jer Cho A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction. [Citation Graph (0, 0)][DBLP ] Conf ] A. Häberli , Piero Malcovati , Henry Baltes , Franco Maloberti An Incremental A/C Converter for Accurate Vector Probe Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Liang Wang , Ching-Chia Chen , Che-Fu Chen A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiang-Ling Li , Chaitali Chakrabarti A New Viterbi Decoder Design for Code Rate K/N . [Citation Graph (0, 0)][DBLP ] Conf ] Arun Raghupathy , Ut-Va Koc , K. J. Ray Liu A Waveront Array for URV Decomposition Updating. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh R. Shanbhag , Gi-Hong Im Pipelined Adaptive IIR Filter Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Pirsch , Johannes Kneip , Karsten Rönner Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Vigyan Singhal , Robert K. Brayton , Carl Pixley Power-Up Delay for Retiming Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jeong-Taek Kong , David Overhauser Combining RC-Interconnect Effects with Nonlinear MOS Macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Hsing Hsieh , Shyh-Jye Jou , Chauchin Su A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeong-Taek Kong , Syed Zakir Hussain , David Overhauser Improving Digital MOS Macromodel Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Zakir Hussain , David Overhauser Automatic Dynamic Mixed-Mode Simulation Through Network Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] P. P. Vaidyanathan , Tsuhan Chen Structures for Time Reversed Inversion in Filter Banks. [Citation Graph (0, 0)][DBLP ] Conf ] See-May Phoong , P. P. Vaidyanathan Efficient Recursive Computation of 1D and 2D-Quincunx IIR Wavelets. [Citation Graph (0, 0)][DBLP ] Conf ] T. Engin Tuncer , Truong Q. Nguyen IIR M-Th Band Filters with Allpass Components. [Citation Graph (0, 0)][DBLP ] Conf ] Sankar Basu , Han-Mook Choi Mermite-like Reduction Method for Design of Perfect Reconstruction Multiband Linear Phase Filter Banks. [Citation Graph (0, 0)][DBLP ] Conf ] P. P. Vaidyanathan , See-May Phoong Reconstruction of Sequences from Nonuniform Samples. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Feng , Hassan Mehrpour , Kwok-Tung Lo , A. E. Karbowiak Two-Layer MPEG Video Coding Algorithm for ATM Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Winzker , Peter Pirsch , Jochen Reimers Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Yanghoon Kim , Chong S. Rim , Byoungki Min A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Chen , Alan N. Willson Jr. A High Accuracy Predictive Logarithmic Motion Estimation Algorithm for Video Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Honken , Feng-Ming Yang , Rainer Laur A HDTV-Suited Architecture for a Fast Full Search Block-Matching Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Dunn , Mark B. Sandler Linearising Sigma-Delta Modulators Using Dither and Chaos. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas P. Borsodi , Behrouz Nowrouzian Closed-Form Solution of Granular Quantization Error for a Class of Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Montgomery Goodson , Bo Zhang , Richard Schreier Proving Stability of Delta-Sigma Modulator Using Invariant Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît R. Veillette , Gordon W. Roberts Bandpass Signal Generation Using Delta-Sigma Modulation Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Pervez M. Aziz , Henrik V. Sorensen , Jan Van der Spiegel Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Johan A. K. Suykens , Joos Vandewalle Generalized Cellular Neural Networks Represented in he NLq [Citation Graph (0, 0)][DBLP ] Conf ] Benzheng Xiao An Algebraic Construct Method for Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Bing J. Sheu , Sa H. Bang , Wai-Chi Fang VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Servando Espejo-Meana , Rafael Domínguez-Castro , Ángel Rodríguez-Vázquez Realization of a CNN Universal Chip in CMOS Technolgy. [Citation Graph (0, 0)][DBLP ] Conf ] R. Yentis Jr. , C. A. Zincke , Mona E. Zaghloul , M. Gaitan Micromachined Display Ouptut for a Cellular Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Timo Veijola , Tapani Ryhänen Model of Capacitive Micromechanical Accelerometer Including Effect of Squeezed Gas Film. [Citation Graph (0, 0)][DBLP ] Conf ] Johan Scholliers , Timo Yli-Pietilä A SPICE-Based Library for Mechatronic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jacek Wojciechowski , Leszek J. Opalski , Krzysztof Zamlynski From Circuit to Mechatronic System Tolerance Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Mann Mixed Energy-Domain Multipoles and Multiports. [Citation Graph (0, 0)][DBLP ] Conf ] Ute Feldmann , Martin Hasler , Wolfgang M. Schwarz Communication by Chaotic Signals: The Inverse System Approach. [Citation Graph (0, 0)][DBLP ] Conf ] R. Lozi Using Filters for Chaotic Synchronization or Communications. [Citation Graph (0, 0)][DBLP ] Conf ] T. L. Carroll Using Filters for Chaotic Synchronization for Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Celka Synchronization of Chaotic Systems Through Parameter Adaptation. [Citation Graph (0, 0)][DBLP ] Conf ] K. Nagaraj Self-Calibration Technique for Pipe-Lined Algorithmic ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Haruo Kobayashi , Hiroshi Sakayori , Tsutomu Tobari , Hiroyuki Matsuura Error Correction Algorithm for Folding/Interpolation ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Mason , John T. Taylor High-Speed, High-Reslution Analogue-To-Digital Conversion Using a Hybrid Electro-Optic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Donald M. Hummels , Wahid Ahmed , F. H. Irons Measurement of Random Sample Time Jitter for ADCs. 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