Conferences in DBLP
Panos Nasiopoulos , Rabab Kreidieh Ward A Hybrid Coding Method for Digital HDTV Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Wai Hong , Yuk-Hee Chan , Wan-Chi Siu An Adaptive Constrained Least Square Approach for Removing Blocking Effect. [Citation Graph (0, 0)][DBLP ] Conf ] Kwok-Tung Lo , Jian Feng New Dyadic Transform for Image Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Chengshan Xiao , David J. Hill , Panajotis Agathoklis On Stability and the Lyapunov Equation for n-Dimensional Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] S. A. Yost , Peter H. Bauer Asymptotic Stability of Linear Shift-Variant Difference Equations with Diamond-Shaped Uncertainties. [Citation Graph (0, 0)][DBLP ] Conf ] Yuval Bistritz Stability Test for 2-D LSI System Via a Unit Circle Test for Complex Polynomials. [Citation Graph (0, 0)][DBLP ] Conf ] Osman Ismail , B. Bandyopadhyay Robust Pole Assignment for Discrete Interval Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Romano Fantacci , M. Forti , A. Liberatore , Stefano Manetti , Mauro Marini Suppression of Spurious Responses for a Class of Neural Networks with Application to Telecommunications Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jack L. Meador Spaciotemporal Neural Networks for Shortest Path Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Kawaguchi , Tamio Todaka A Neural Network for the Scheduling Problem in High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-Hyun Cho , Weon-Ook Kim , Hyun-Koo Kang A New Approach for Improving the Convergence Performance of Global Optimization Problems. [Citation Graph (0, 0)][DBLP ] Conf ] R. Belmans , K. Hameyer Combining Circuit Theory and Numerical Field Calculations in Designing Mini-Mechatronic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kecskemethy Extending the Transmission-Element Model for Mechanical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Domine Leenaerts , Arjan J. Leeuwenburgh , G. G. Persoon , H. J. Reitsma A New Architecture for a Cyclic Algorithmic D/A Converter. [Citation Graph (0, 0)][DBLP ] Conf ] P. P. Vervoort , R. F. Wassenaar A CMOS Rail-to-Rail Linear VI-Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Sitthichai Pookaiyaudom , Jirayuth Mahattanakul A 3.3 Volt High-Frequency Capacitorless Electronically-Tunable Log-Domain Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Chung-Yu Wu , Hun-Hsien Chang , Tao Cheng , Tain-Shun Wu Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Thomsen , Robert Lindquist , Jeffrey H. Kulick , Patrick Nasiatka , Gregory Nordin , Stephen Kowel A Pixel Scale Digital to Analog Converter for Liquid Crystal on VLSI Displays. [Citation Graph (0, 0)][DBLP ] Conf ] Geir E. Sæther , Chris Toumazou , Gaynor E. Taylor , Kevin R. Eckersall , Ian M. Bell Concurrent Self Test of Switched Current Circuits Based on the S2 I-Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Maloberti , S. Brigati , Giuseppe Caiulo , Guido Franchi , A. Bigongiari An Analog High-Speed Wide-Range Programmable Monostable Multivibrator. [Citation Graph (0, 0)][DBLP ] Conf ] Girish N. Patel , Stephen P. DeWeerth An Analog VLSI Loser-Take-All Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Paul D. Walker , Michael M. Green A Loser-Take-All Error Amplifier for DC Power Supply Control. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew G. Dempster , Malcolm D. Macleod Comparison of IIR Filter Structure Complexities Using Multiplier Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ashraf Alkhairy On IIR Filter Design. [Citation Graph (0, 0)][DBLP ] Conf ] T. S. Ng , Joe F. Chicharo IIR Notch Filtering - Comparisons of Four Adaptive Algorithms for Frequency Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] J. L. Sullivan , J. W. Adams A Nonlinear Optimization Algorithm for Asymmetric FIR Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] G. Deng , L. Cahill Isotropic Quadratic Filter Design Using the Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Joon Tae Kim , Woo Jin Oh , Yong Hoon Lee Design of Non-Uniformly Spaced Linear Phase FIR Filters Using Mixed Integer Linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Simon M. Kershaw , Steve Summerfield , Mark B. Sandler On Sigma-Delta Signal Processing Remodulator Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] François Moreau de Saint-Martin , Pierre Siohan Design of Optimal Linear-Phase Transmitter and Receiver Filters for Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Dickmann , N. J. Fliege Digital Signal Processing for Multi-Carrier Data Transmission on Phase-Controlled Power Lines with Nonlinearities. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas R. Frey On Chaotic Digital Encoding and Generalized Inverses. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. GadelRab , James A. Barby , Savvas G. Chamberlain An Architecture for Integrated Reliability Simulators Using Analog Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth J. Brauer , Sung-Mo Kang Estimating Node Voltages in Bipolar Circuits Using Linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dolle Analysis of Simultaneous Switching Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Rezai , Mabo Robert Ito , P. D. Lawrence Modeling and Simulation of Hybrid Control Systems by Global Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Penzo , Donatella Sciuto , Cristina Silvano GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuo Nishi , Yuji Kawane An Extension of the Tadeusiewicz Method for Finding Bounds on All Solutions of Piecewise-Linear Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel J. Gómez , Sherif H. K. Embabi , Edgar Sánchez-Sinencio , Martin C. Lefebvre A Nonlinear Macromodel for CMOS OTAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yongjoo Kim , Youngsoo Shin , Kyuseok Kim , Jaehee Won , Kiyoung Choi Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. [Citation Graph (0, 0)][DBLP ] Conf ] João Camara , Helena Sarmento Tool Management in an Electronic CAD Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Andrew , Seraphim Poriazis Design of Synchronous Circuits with Multiple Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Mankoo Lee , Wing-Il Sze , Chii-ming M. Wu Static Noise Margin and Soft-Error Rate Simulations for Thin Film Transistor Cell Stability in a 4 Mbit SRAM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Patrik Larsson Skew Safety and Logic Flexibility in a True Single Phase Clocked System. [Citation Graph (0, 0)][DBLP ] Conf ] W. Eatherton , J. Kelly , T. Schiefelbein , H. Pottinger , L. R. Mullin , R. Ziegler An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Soufi , Yvon Savaria , Bozena Kaminska On Using Partial Reset for Pseudo-Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Kuskie , Bo Zhang , Richard Schreier A Decimation Filter Architecture for GHz Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Lightstone , Eduardo Abreu , Sanjit K. Mitra , Kaoru Arakawa State-Conditioned Rank-Ordered Filtering for Removing Impulse Noise in Images. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Taguchi , Mitsuhiko Meguro Adaptive L-Filters Based on Fuzzy Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xu , Wu-Sheng Lu , Andreas Antoniou Design of Perfect Reconstruction QMF Banks by a Null-Space Projection Method. [Citation Graph (0, 0)][DBLP ] Conf ] Esam Abdel-Raheem , Fayez El Guibaly , Andreas Antoniou Design of Low-Delay Perfect-Reconstruction FIR Filter Banks for Tree-Structured Subband Coders. [Citation Graph (0, 0)][DBLP ] Conf ] Q. S. Gu , M. N. S. Swamy , Leon C. K. Lee , M. Omair Ahmad IIR Digital Filters for Sampling Structure Conversion and Deinterlacing of Video Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Yuang-Ming Hsu , Vincenzo Piuri , Earl E. Swartzlander Jr. Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Tang , Hung Chang Lin Defuzzifier Circuits Using Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP ] Conf ] Howard C. Card , Dean K. McNeill , Christian R. Schneider , Roland S. Schneider The Impact of VLSI Fabrication on Neural Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Brannon C. Harris , Stephen P. DeWeerth Analog Encoding Circuits for a Digital CMOS Neural Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuyuki Sanada , Toshimichi Saito Response Characteristic from an Artificial Hysteresis Neuron. [Citation Graph (0, 0)][DBLP ] Conf ] Hongtao Lu , Luxi Yang , Wang Baoyun , Zhenya He A New Type of Chaotic Attractor with Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kenya Jin'no Bifurcation Phenomena from a Simple Hysteresis Network. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Itoh , Hiroyuki Murakami , Leon O. Chua Signal Transmission through a Chain of Chua's Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ljupco Kocarev Chaos Synchronization of High-Dimensional Dynamical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Toshimichi Saito , Hiroyuki Torikai , Kenya Jin'no Synchronization and Control of Chaos by Occasional Linear Connection. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin M. Cuomo Systematic Synthesis Procedures for High-Dimensional Chaotic Systems: Methods and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Seyfi S. Bazarjani , W. Martin Snelgrove Low Voltage SC Circuit Design with Low-Vt MOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yu Wu , Wei-Shinn Wey , Tsai-Chung Yu A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock Boosters. [Citation Graph (0, 0)][DBLP ] Conf ] Hirokazu Yoshizawa , Gabor C. Temes High-Linearity Switched-Capacitor Circuits in Digital CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua C. Park , Rohit Mittal , Kimberly C. Bracken , L. Richard Carley , David J. Allstot High-Speed CMOS Current-Mode Equalizers. [Citation Graph (0, 0)][DBLP ] Conf ] K. A. Kozma , David A. Johns , Adel S. Sedra An Approach for Tuning High-Q Continuous-Time Bandpass Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Gilles Privat , Frédéric Robin , Marc Renaudin , Bachar El Hassan A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kuei-Ming Lu , Keikichi Tamaru A New Algorithm for Sorting Problem with Reformed CAM. [Citation Graph (0, 0)][DBLP ] Conf ] Kyumyung Choi , Steven P. Levitan Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Apoorv Srivastava , Yong-Seon Koh , Barton Sano , Alvin M. Despain 190-MHz CMOS 4-Kbyte Pipelined Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Duhalde , Alain Greiner , Frédéric Pétrot A High Performance Modular Embedded ROM Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Ter Kuo , Lung-Tien Liu , Chung-Kuan Cheng Finite State Machine Decomposition for I/O Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongli He , Dian Zhou Optimization of VLSI Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Niraj K. Jha An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Calvin J. A. Hsia , C. Y. Roger Chen Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] D. Mueller , August Kaelin A Hybrid HDSL Echo Canceler. [Citation Graph (0, 0)][DBLP ] Conf ] Byungjin Chun , Beomsup Kim , Yong Hong Lee Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Doblinger Performance Analysis of an Adaptive Subspace Filter for Signal Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Jae Ha Yoo , Sung Ho Cho , Dae Hee Youn A Lattice/Transversal Joint (LTJ) Structure for an Acoustic Echo Canceller. [Citation Graph (0, 0)][DBLP ] Conf ] Tracie A. Schirtzinger , W. Kenneth Jenkins Designing Adaptive Equalizers Based on the Constant Modulus Error Criterion. [Citation Graph (0, 0)][DBLP ] Conf ] Pen-Shu Yeh , Warner H. Miller A Real-Time Lossless Data Compression Technology for Remote-Sensing and Other Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Giridhar Mandyam , Nasir Ahmed , Samuel D. Stearns A Two-Stage Scheme for Lossless Compression of Images. [Citation Graph (0, 0)][DBLP ] Conf ] Yousef W. Nijim , Wasfy B. Mikhael , Samuel D. Stearns Lossless Compression of Seismic Signals Using Least Square Frequency Domain Pole-Zero Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Coffey , Delores M. Etter Image Coding with the Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory M. Cooley , Terri S. Fiez , Bryan Buchanan PWM and PCM Techniques for Control of Digitally Programmable Switching Power Supplies. [Citation Graph (0, 0)][DBLP ] Conf ] Motoki Fujii , Tadashi Suetugu , Hirotaka Koizumi , Kokichi Shinoda , Shinsaku Mori Resonant dc/dc Converter with Class E Inverter and Class E Synchronous Rectifier Using Thinned-Out Method. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Chung , Adrian Ioinovici Large-Signal Stability of PWM Switching Regulators. [Citation Graph (0, 0)][DBLP ] Conf ] A. Abur , D. Shirmohammadi , C. S. Cheng Estimation of Switch Statuses for Radical Power Distribution Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Weijun Ji , Vaithianathan Venkatasubramanian Dynamics of Minimal Power System Model - Invariant Tori and Quasi-Periodic Motions. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Ye , Anthony N. Michel , Kaining Wang Qualitative Analysis of Hopfield Neural Nets with Delays: Global and Local Results. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Bhaya , Eugenius Kaszkurewicz , V. S. Kozyakin Existence and Stability of a Unique Equilibrium in Continuous-Valued Discrete-Time Asynchronous Hopfield Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Huanglin Zeng , Roman W. Swiniarski On Dynamics of a Learning Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] S. Jankowski , Andrzej Lozowski , Jacek M. Zurada Multivalued Neural Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhisa Kanaya , Masako Takahira , Toshirou Watanabe , Cong-Kha Pham , Mamoru Tanaka Associative Dynamics of Competitive Cellular Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Jaime Ramírez-Angulo , Kevin Treece , P. Andrews , T. Choi Current-Mode and Voltage-Mode VLSI Fuzzy Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuho Tamano Development of a Hyper-Parallel Optical Fuzzy-Neural Network Using Images. [Citation Graph (0, 0)][DBLP ] Conf ] Bing J. Sheu , Robert C. Chang , Tony H. Wu , Sa H. Bang VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Apollo Q. Fong , Ajay Kanji , Edgar Sánchez-Sinencio , José Pineda de Gyvez A Universal Interface Between PC and Neural Networks Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Veda-Pineda , Sergio D. Cabrera , Yi-Chieh Chang VLSI Implementation of a Wavelet Image Compression Technique Using Replicated Coding/Decoding Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Guanrong Chen , Xiaoning Dong Identification and Control of Chaotic Systems: An Artificial Neural Network Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mirko Paskota Targeting in Chaotic Dynamical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ira B. Schwartz Ioana Triandaf Detecting Motion on Center Manifolds from a Time Series - An Example. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé Dedieu , Maciej Ogorzalek Signal Coding and Compression Based on Chaos Control Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] James A. Cherry , W. Martin Snelgrove Analog Filter Banks with Low Intermodulation Distortion. [Citation Graph (0, 0)][DBLP ] Conf ] F. Yang , Christian C. Enz , D. Python A New BiCMOS Low-Voltage and Low-Distortion OTA for Continuous-Time Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Toumazou , Alison Payne , Sitthichai Pookaiyaudom The Active-R Filter Technique Applied to Current-Feedback Op-Amps. [Citation Graph (0, 0)][DBLP ] Conf ] M. Rinne , T. Jarske , Hannu Tenhunen , Olli Vainio , Yrjö Neuvo Noise Suppression System Integration Using an Analog Allpass Filter Bank. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Tae Jung , Eun Sei Park , Jung Sik Kim , Chu Shik Jhon Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Aurobindo Dasgupta , Ramesh Karri Synthesis of Reliable Application Specific Heterogeneous Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Yong Lee , Eugene Shragowitz Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe F. Baake , Sorin A. Huss Logic Reduction in Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xinhui Niu , Jay B. Brockman A Bayesian Approach to Variable Screening for Modeling the IC Fabrication Process. [Citation Graph (0, 0)][DBLP ] Conf ] Jacek Wojciechowski , Leszek J. Opalski , Krzysztof Zamlynski Applications of the Piecewise Ellipsoidal Approximation to the Design of Nonlinear Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lluis Ribas , Jordi Carrabina Symbolic Analysis for Fault Detection in Switch-Level Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Seth Chaiken , Paliath Narendran The All-Minors VCCS Matrix Tree Theorem, Half-Resistors and Applications in Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fukumoto , Hajime Kubota , Shigeo Tsujii Improvement in Stability and Convergence Speed on Normalized LMS Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Ernst , August Kaelin Analysis of the LMS Algorithm with Delayed Coefficient Update. [Citation Graph (0, 0)][DBLP ] Conf ] Mariane R. Petraglia Convergence Analysis of a Subband Adaptive Filter Structure. [Citation Graph (0, 0)][DBLP ] Conf ] K. A. Mayyas , Tyseer Aboulnasr Leaky LMS: A Detailed Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard Coutu , Monique Fargues Lossless Compression of Ultra Wideband Radar Using Adaptive Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Ramaswamy , Wasfy B. Mikhael Development of a Near Lossless Image Compression Technique Using Mixed Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] F. Livingston , N. Magotra , S. Stearns , W. McCoy Real-Time Implementation Concerns for Lossless Waveform Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Mann Circuit Model of Energy-Storing Transducers. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Ying Kuo , Ching Chuan Kuo , Mei Shong Kuo Novel Transmission-Line Collection Systems for Photovoltaic Power. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Pai , Peter W. Sauer , A. Y. Kulkarni A Preconditioned Iterative Solver for Dynamic Simulation of Power Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dongjin Lee , Jeongwon Lee Simulation of Transmission Lines with Frequency Dependent Lossed By Indirect Numerical Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Donham , Jan Van der Spiegel , Paul Mueller , Z. Walton Real Time Feature Extraction of Acoustic Signals with an Analog Neural Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Sammy Siu , Ching-Haur Chang , Che-Ho Wei Square-Root Recursive Prediction Error Algorithm for Perceptron-Based Adaptive Equalization Over Frequency Selective Fading Channel. [Citation Graph (0, 0)][DBLP ] Conf ] D. Bhattacharya , Andreas Antoniou Design of 2-D FIR Filters by Feedback Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Csaba Rekeczky , Akio Ushida , Tamás Roska Diminishment and Enlargement of Binary Pictures Using Slightly Space Variant Cellular Neural Network Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Rong-Chung Chen , Pao-Ta Yu An Optimal Design of Fuzzy (m, n) Rank Order Filtering with Hard Decision Neural Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Tamás Roska , Leon O. Chua , Ákos Zarándy Translating Neuromorphic CNN Visual Models to the Analogic Visual Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Yamakawa A Survey on Fuzzy Information Processing Hardware Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Charles C. Hsu , Jinghua Ding , Mona E. Zaghloul An Image Discrete Wavelet Transform and the Hardware Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Gunhee Han , Edgar Sánchez-Sinencio A General Purpose Discrete-Time Multiplexing Neuron-Array Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] P. E. Pace , J. L. Schafer Decimation of Encoding Errors in an Optimum SNS Folding ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Bruun , Peter Shah Dynamic Range of Low-Voltage Cascode Current Mirrors. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuhiro Sugimoto A 1.6V 10-Bit 20MHz Current-Mode Sample and Hold Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Denise M. Wilson , Stephen P. DeWeerth Winning Isn't Everything. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik T. Jensen , Ian Galton A Robust Parallel Delta-Sigma A/D Converter Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw Szczepanski , Jacek Jakusz , Rolf Schaumann A Linear CMOS OTA for VHF Applications. [Citation Graph (0, 0)][DBLP ] Conf ] D. R. Webster , David G. Haigh , Anthony E. Parker Novel Circuit Synthesis Technique Using Short Channel GaAs Fets Giving Reduced Intermodulation Distortion. [Citation Graph (0, 0)][DBLP ] Conf ] Ute Feldmann , Alexander Rahm , Michiko Miura-Mattausch Benchmarking MOS Transistor Models with Respect to Capacitances and Charges for Analog Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoning Nie , Rolf Unbehauen Parallel Processing of Two-Dimensional Sequences Using 2-D Denominator-Separable digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Shatnawi , M. Omair Ahmad , M. N. S. Swamy Rate-Optimal Static Scheduling of DSP Data Flow Graphs onto Multiprocessors using Circuit Contraction. [Citation Graph (0, 0)][DBLP ] Conf ] Alvin W. Su , Shyi-Ching Liau A Class of Linear Cyclic-Invariant Filter for Parallel Filtering of Discrete-Time Signals. [Citation Graph (0, 0)][DBLP ] Conf ] G. Angelopoulos , Ioannis Pitas Parallel Digital Signal Filtering on Barrel Shifter Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Werter , Alan N. Willson Jr. Automated Programming of a Ring-Structured Multiprocessor Digital Filter IC. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Xing Zheng , Ba-Ngu Ba-Ngu Vo , Antonio Cantoni , Kok Lay Teo Improved Recursive Procedures for Envelope-Constrained Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] C. Y. Chung , S. C. Ng , Shu Hung Leung , Andrew Luk A Variable Step Size Algorithm with Generate-and Evaluate Function. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Gut , Peter Kreier , George S. Moschytz Trellis-Based Deconvolution of Ultrasonic Echoes. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Georg Brachtendorf , G. Welsch , Rainer Laur Fast Simulation of the Steady-State of Circuits by the Harmonic Balance Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Kan Cheng , Sung-Mo Kang Chip-Level Thermal Simulator to Predict VLSI Chip Temperature. [Citation Graph (0, 0)][DBLP ] Conf ] Shyh-Jye Jou , Kou-Fong Liu , Chauchin Su Circuits Design Optimization Using Symbolic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Osman Ismail , B. Bandyopadhyay Model Reduction of Linear Interval Systems Using Padé Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Katarzyna Opalska , Leszek J. Opalski Decomposition-Based Model Parameter Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] John I. Sewell , Z. Q. Shang Accurate Semi-Symbolic Analysis of Large Non-Ideal Switched Linear Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan A. Maio , Flavio G. Canavero Differential-Difference Equations for the Transient Simulation of Lossy MTLs. [Citation Graph (0, 0)][DBLP ] Conf ] K. N. Balasubramanya Murthy , C. Siva Ram Murthy A New Parallel Algorithm for Solving Sparse Linear Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yimin Zhang , Armen H. Zemanian Contributions of Corner Singularities of the Capacitance of Interconnections Wires. [Citation Graph (0, 0)][DBLP ] Conf ] Ayman Elnaggar , Hussein M. Alnuweiri , Mabo Robert Ito Highly Parallel VLSI Architectures for Linear Convolution. [Citation Graph (0, 0)][DBLP ] Conf ] An-Nan Suen , Jhing-Fa Wang , Yuen-Lin Chiang A Cepstrum Chip: Architecture and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Wenzler , Ernst Lüder New Structures for Complex Multipliers and Their Noise Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Soderstrand , Kamal Al-Marayati VLSI Implementation of Very-High-Order FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Fu , Keshab K. Parhi Two VLSI Design Advances in Arithmetic Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Terence Wang , Chin-Liang Wang A New Block Adaptive Filtering Algorithm for Decision-Feedback Equalization of Multipath Fading Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Günter Rösel , Norbert J. Fliege Transmultiplexer Filter Banks with Extremely Low Crosstalk and Intersymbol Interference. [Citation Graph (0, 0)][DBLP ] Conf ] Greg J. Erker , David E. Dodds , Witold A. Krzymien Digital Loop Extension Using Mid Span Amplification. [Citation Graph (0, 0)][DBLP ] Conf ] Adil Benyassine , Ali N. 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