Conferences in DBLP
Arun Ravindran , Anup Savla , Jennifer Leonard Digital error correction and calibration of gain non-linearities in a pipelined ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal El-Sankary , Mohamad Sawan A new digital background calibration technique for pipelined ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Tae-Hwan Oh , Ho-Young Lee , Ho-Jin Park , Jae-Whui Kim A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Kinyua , Franco Maloberti , William Gosney Digital background auto-calibration of DAC non-linearity in pipelined ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bogner A 28mW 10b 80MS/s pipelined ADC in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Jader A. De Lima , Fernando M. Alcaide On designing linearly tunable high-Q OTA-C filters with low sensitivity. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Serra-Graells , Xavier Redondo Exact design of all-MOS log filters. [Citation Graph (0, 0)][DBLP ] Conf ] Pamela Abshire , Eric Liu Wong , Yiming Zhai , Marc H. Cohen Adaptive log domain filters using floating gate transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Chawla , Haw-Jing Lo , Arindam Basu , Paul E. Hasler , Bradley A. Minch A fully programmable log-domain bandpass filter using multiple-input translinear elements. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Ming Chang 6.61MHz to 317MHz nth-order current-mode low-pass and high-pass OTA-only-without-C filter. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Jung-Sheng Chen , Ching-Yun Chu A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Tajalli , Seyed Mojtaba Atarodi , Abbas Khodaverdi , Farzad Sahandi Esfanjani Design and optimization of a high PSRR CMOS bandgap voltage reference. [Citation Graph (0, 0)][DBLP ] Conf ] Chi Yat Leung , Ka Nang Leung , Philip K. T. Mok Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference. [Citation Graph (0, 0)][DBLP ] Conf ] Laleh Najafizadeh , Igor M. Filanovsky Towards a sub-1 V CMOS voltage reference. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinando Bedeschi , Edoardo Bonizzoni , Andrea Fantini , Claudio Resta , Guido Torelli A low-power low-voltage MOSFET-only voltage reference. [Citation Graph (0, 0)][DBLP ] Conf ] Hanjun Jiang , Haibo Fei , Degang Chen , Randall L. Geiger A background digital self-calibration scheme for pipelined ADCs based on transfer curve estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Savla , Jennifer Leonard , Arun Ravindran A novel queuing architecture for background calibration of pipeline ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , Omid Shoaei A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter]. [Citation Graph (0, 0)][DBLP ] Conf ] Babak Nejati , Omid Shoaei A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Movahedian , Meysam Azin , Mehrdad Sharif Bakhtiar A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range. [Citation Graph (0, 0)][DBLP ] Conf ] Tom J. Kazmierski , Fazrena A. Hamid Behavioral modelling of RF filters in VHDL-AMS for automated architectural and parametric optimization. [Citation Graph (0, 0)][DBLP ] Conf ] José L. Ausín , J. Francisco Duque-Carrillo , Guido Torelli , Miguel Angel Domínguez A design strategy for area efficient high-order high-Q SC filters. [Citation Graph (0, 0)][DBLP ] Conf ] Drazen Jurisic , George S. Moschytz , Neven Mijat Low active-sensitivity allpole active-RC filters using impedance tapering. [Citation Graph (0, 0)][DBLP ] Conf ] Taner Sumesaglam , Aydin I. Karsilayan Digital tuning of analog bandpass filters based on envelope detection. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Graham , Paul D. Smith , Richard Ellis , Ravi Chawla , Paul E. Hasler A programmable bandpass array using floating-gate elements. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Shi , Yan Wah Chia Design of a SiGe low-noise amplifier for 3.1-10.6 GHz ultra-wideband radio. [Citation Graph (0, 0)][DBLP ] Conf ] Su-Tarn Lim , John R. Long A feedforward compensated high-linearity differential transconductor for RF applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Bagga , Giuseppe de Vita , Sandro A. P. Haddad , Wouter A. Serdijn , John R. Long A PPM Gaussian pulse generator for ultra-wideband communications. [Citation Graph (0, 0)][DBLP ] Conf ] Xuejin Wang , Aykut Dengi , Sayfe Kiaei A high IIP3 X-band BiCMOS mixer for radar applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jinho Park , David J. Allstot A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro M. Figueiredo , João C. Vital Termination of averaging networks in flash ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Cheng Huang , Jieh-Tsorng Wu A statistical background calibration technique for flash analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Sall , Mark Vesterbacka , K. Ola Andersson A study of digital decoders in flash analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Ovidiu Carnu , Adrian Leuciuc Optimal offset averaging for flash and folding A/D converters. [Citation Graph (0, 0)][DBLP ] Conf ] Quentin Diduck , Martin Margala 6-bit low power low area frequency modulation based flash ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Igor M. Filanovsky , Arie van Staveren , Chris J. M. Verhoeven Synthesis of amplifier transfer function using time-domain response. [Citation Graph (0, 0)][DBLP ] Conf ] Sandro A. P. Haddad , Nanko Verwaal , Richard Houben , Wouter A. Serdijn Optimized dynamic translinear implementation of the Gaussian wavelet transform. [Citation Graph (0, 0)][DBLP ] Conf ] Mladen Vucic , Goran Molnar , Hrvoje Babic Method for equalizer design based on time-domain symmetry. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Gómez-Garcia , José I. Alonso Exact synthesis of bandpass responses using an isolated cascade connection of same order lowpass and highpass filters. [Citation Graph (0, 0)][DBLP ] Conf ] Yannis P. Tsividis Mixing domains in signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Romanò , Salvatore Levantino , Andrea Bonfanti , Carlo Samori , Andrea L. Lacaita Phase noise and accuracy in quadrature oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Luís Bica Oliveira , Jorge R. Fernandes , Igor M. Filanovsky , Chris J. M. Verhoeven A 2.4 GHz CMOS quadrature LC-oscillator/mixer. [Citation Graph (0, 0)][DBLP ] Conf ] Paola Tortori , Davide Guermandi , Eleonora Franchi , Antonio Gnudi Quadrature VCO based on direct second harmonic locking. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Magierowski , Krzysztof Iniewski , Stefan Zukotynski A wideband LC-VCO with enhanced PSRR for SOC applications. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksandar Tasic , Wouter A. Serdijn , John R. Long DCS1800/WCDMA adaptive voltage-controlled oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Lourans Samid , Patrick Volz , Yiannos Manoli A dynamic analysis of a latched CMOS comparator. [Citation Graph (0, 0)][DBLP ] Conf ] Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng Generalizations of adjoint networks technique for RLC interconnects model-order reductions. [Citation Graph (0, 0)][DBLP ] Conf ] Shyam Subramanian , David V. Anderson , Paul E. Hasler Synthesis of static multiple input multiple output MITE networks. [Citation Graph (0, 0)][DBLP ] Conf ] Makeswaran Loganathan , Suvarcha Malhotra , Pamela Abshire Information capacity and power efficiency in operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Kumar , Sandip Tiwari A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] HaiBin Huang , Ezz I. El-Masry An 89dB low-power CMOS Sigma Delta modulator for Bluetooth application. [Citation Graph (0, 0)][DBLP ] Conf ] José M. García-González , Sara Escalera , José Manuel de la Rosa , Oscar Guerra , Fernando Manuel Medeiro Hidalgo , Rocio del Río , Maria Belen Pérez-Verdú , Ángel Rodríguez-Vázquez A 0.35µm CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 Sigma Delta modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Olujide A. Adeniran , Andreas Demosthenous , Chris Clifton , Sam Atungsiri , Randeep Soin A CMOS low-power ADC for DVB-T and DVB-H systems. [Citation Graph (0, 0)][DBLP ] Conf ] Angelo W. Pereira , Daniel J. Allen , Paul E. Hasler A 0.5µm CMOS programmable discrete-time Delta-Sigma modulator with floating gate elements. [Citation Graph (0, 0)][DBLP ] Conf ] Sami Karvonen , Tom A. D. Riley , Juha Kostamovaara A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR. [Citation Graph (0, 0)][DBLP ] Conf ] Omid Oliaei Spectral analysis of signals experiencing nonstationary stochastic time-shifts. [Citation Graph (0, 0)][DBLP ] Conf ] Reuben Wilcock , Bashir M. Al-Hashimi Power-conscious design methodology for class-A switched-current wave filters. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf M. Philipp , Ralph Etienne-Cummings Low power current rectifiers for large scale current-mode signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Corbishley , Esther Rodríguez-Villegas , Chris Toumazou An ultra-low power analogue directionality system for digital hearing aids. [Citation Graph (0, 0)][DBLP ] Conf ] Chengming He , Kuangming Yap , Degang Chen , Randall L. Geiger NTH order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient. [Citation Graph (0, 0)][DBLP ] Conf ] Jangsup Yoon , William R. Eisenstadt Lumped passive circuits for 5GHz embedded test of RF SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Qizhang Yin , Robert M. Fox , William R. Eisenstadt A translinear-based RF RMS detector for embedded test. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongjun Yu , Degang Chen , Randall L. Geiger The SRE/SRM approach for spectral testing of AMS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Levine , Gordon W. Roberts A calibration technique for a high-resolution flash time-to-digital converter. [Citation Graph (0, 0)][DBLP ] Conf ] Sara Escalera , José M. García-González , Oscar Guerra , José Manuel de la Rosa , Fernando Manuel Medeiro Hidalgo , Maria Belen Pérez-Verdú , Ángel Rodríguez-Vázquez An alternative DFT methodology to test high-resolution Sigma Delta modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Igor M. Filanovsky Reactance network shaping a sinusoidal pulse with sinusoidal envelope of finite duration. [Citation Graph (0, 0)][DBLP ] Conf ] Ernst Goepel Active RC networks: what benefit is there in having conjugate real zeros in the second-order transfer function? [Citation Graph (0, 0)][DBLP ] Conf ] Timo Rahkonen , Jyri Kortekangas Mixed-mode parameter analysis of fully differential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Herminio Martínez , Eva Vidal , Eduard Alarcón , Alberto Poveda Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuo Nishi , Masato Ogata Simultaneous realization of Z/sub 21//Z/sub 11/ and Y/sub 21/ of an RC two-port. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil Rafeeque , Vinita Vasudevan An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Clara , Andreas Wiesbauer , Wolfgang Klatzer Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Keller , Yiannos Manoli , Friedel Gerfers A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Chen , Georges G. E. Gielen Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters. [Citation Graph (0, 0)][DBLP ] Conf ] Jussi Pirkkalaniemi , Marko Kosunen , Mikko Waltari , Kari Halonen A digital calibration for a 16-bit, 400-MHz current-steering DAC. [Citation Graph (0, 0)][DBLP ] Conf ] Teresa Serrano-Gotarredona , Rafael Serrano-Gotarredona , Bernabé Linares-Barranco Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu Ravinuthula , John G. Harris Time-based arithmetic using step functions. [Citation Graph (0, 0)][DBLP ] Conf ] Ethan Farquhar , Paul E. Hasler A bio-physically inspired silicon neuron. [Citation Graph (0, 0)][DBLP ] Conf ] Ethan Farquhar , David N. Abramson , Paul E. Hasler A reconfigurable bidirectional active 2 dimensional dendrite model. [Citation Graph (0, 0)][DBLP ] Conf ] Christal Gordon , Ethan Farquhar , Paul E. Hasler A family of floating-gate adapting synapses based upon transistor channel models. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Shih-Lun Chen , Chia-Sheng Tsai A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes. [Citation Graph (0, 0)][DBLP ] Conf ] Susanta Sengupta , Kanan Saurabh , Phillip E. Allen A process, voltage, and temperature compensated CMOS constant current reference. [Citation Graph (0, 0)][DBLP ] Conf ] Chua-Chin Wang , Yih-Long Tseng , Tzung-Je Lee , Ron Hu High-PSR bias circuitry for NTSC sync separation. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar Mauricio Camacho-Galeano , Carlos Galup-Montoro , Márcio C. Schneider Design of an ultra-low-power current source. [Citation Graph (0, 0)][DBLP ] Conf ] Tobi Delbrück , André van Schaik Bias current generators with wide dynamic range. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Pastre , Maher Kayal High-precision DAC based on a self-calibrated sub-binary radix converter. [Citation Graph (0, 0)][DBLP ] Conf ] Jeroen De Maeyer , Pieter Rombouts , Ludo Weyten Addressing static and dynamic errors in bandpass unit element multibit DAC's. [Citation Graph (0, 0)][DBLP ] Conf ] Saeed Saeedi , Saeid Mehrmanesh , Seyed Mojtaba Atarodi , Hesam Amir Aslanzadeh A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hsing Cheng , Tsung-Shen Chen , Chia Ming Tu A 14-bit, 200 MS/s digital-to-analog converter without trimming. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo J. Serrano , Paul E. Hasler A floating-gate DAC array. [Citation Graph (0, 0)][DBLP ] Conf ] Bernabé Linares-Barranco , Teresa Serrano-Gotarredona , Rafael Serrano-Gotarredona , Luis A. Camuñas On leakage current temperature characterization using sub-pico-ampere circuit techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Inchang Seo , Robert M. Fox Comparison of quasi-/pseudo-floating gate techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sai-Weng Sin , Seng-Pan U. , Rui Paulo Martins A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo J. Serrano , Paul D. Smith , Haw-Jing Lo , Ravi Chawla , Tyson S. Hall , Christopher M. Twigg , Paul E. Hasler Automatic rapid programming of large arrays of floating-gate elements. [Citation Graph (0, 0)][DBLP ] Conf ] Bernabé Linares-Barranco , Teresa Serrano-Gotarredona , Rafael Serrano-Gotarredona , Gustavo Vicente-Sánchez On mismatch properties of MOS and resistors calibrated ladder structures. [Citation Graph (0, 0)][DBLP ] Conf ] Ilkka Nissinen , Juha Kostamovaara A low voltage CMOS constant current-voltage reference circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ka Nang Leung , Philip K. T. Mok , Sai Kit Lau A low-voltage CMOS low-dropout regulator with enhanced loop response. [Citation Graph (0, 0)][DBLP ] Conf ] Walter Aloisi , Stello Matteo Billé , Gaetano Palumbo Low-voltage linear voltage regulator suitable for memories. [Citation Graph (0, 0)][DBLP ] Conf ] Vladislav Y. Potanin , Elena E. Potanina High-voltage-tolerant power supply in a low-voltage CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Preetam Tadeparthy A CMOS bandgap reference with correction for device-to-device variation. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter Rombouts , Jeroen De Maeyer , Johan Raman , Ludo Weyten Systematic design of double-sampling Sigma Delta ADC's with modified NTF. [Citation Graph (0, 0)][DBLP ] Conf ] Maurits Ortmanns , Markus Kuderer , Yiannos Manoli , Friedel Gerfers A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. [Citation Graph (0, 0)][DBLP ] Conf ] Ut-Va Koc , Jaesik Lee Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wern Ming Koe , Franco Maloberti Feed-forward path and gain-scaling - a swing and distortion reduction scheme for second order sigma-delta modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Jannik Hammel Nielsen , Erik Bruun A low-power 10-bit continuous-time CMOS Sigma Delta A/D converter. [Citation Graph (0, 0)][DBLP ] Conf ] Belén Calvo , Santiago Celma , Maria Teresa Sanz CMOS digitally programmable cell for high frequency amplification and filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyuki Nakayama , Toshihiko Yamasaki , Tadashi Shibata Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. [Citation Graph (0, 0)][DBLP ] Conf ] Jacqueline S. Pereira , Antonio Petraglia , Franco Maloberti A 0.18µm CMOS SC lowpass filter for Bluetooth channel selection. [Citation Graph (0, 0)][DBLP ] Conf ] Shelly Xiao , José Silva , Un-Ku Moon , Gabor C. Temes A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sami Karvonen , Tom A. D. Riley , Sami Kurtti , Juha Kostamovaara A 50-MHz BiCMOS quadrature charge sampler and complex bandpass SC filter for narrowband applications. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelouahab Djemouai , Mohamad Sawan New CMOS current-mode amplitude shift keying demodulator (ASKD) dedicated for implantable electronic devices. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Arnaud , Carlos Galup-Montoro A fully integrated 0.5-7 Hz CMOS bandpass amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy G. Constandinou , Julius Georgiou , Chris Toumazou A nano-power tuneable edge-detection circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Fausto Borghetti , Lorenzo Farina , Piero Malcovati , Franco Maloberti A high speed and low power CMOS current comparator for photon counting systems. [Citation Graph (0, 0)][DBLP ] Conf ] Harpreet S. Narula , John G. Harris VLSI potentiostat for amperometric measurements for electrolytic reactions. [Citation Graph (0, 0)][DBLP ] Conf ] Shubha Bommalingaiahnapallya , Ramesh Harjani Low power implementation of an n-tone Sigma Delta converter. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Yavari , Omid Shoaei Low-voltage sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhiko Yagyu , Akinori Nishihara Fast and efficient algorithm to design noise-shaping FIR filters for high-order overload-free stable sigma-delta modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Kye-Shin Lee , Yunyoung Choi , Franco Maloberti Domino free 4-path time-interleaved second order sigma-delta modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph Mason , Chris DeVries , Eugene Ivanov An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz. [Citation Graph (0, 0)][DBLP ] Conf ] Chengming He , Le Jin , Degang Chen , Randall L. Geiger Robust design of high gain amplifiers using dynamical systems and bifurcation theory. [Citation Graph (0, 0)][DBLP ] Conf ] Gaetano Palumbo , Salvatore Pennisi Harmonic distortion in three-stage nested-Miller-compensated amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Petrie , Tianxue Sun , Matt Miller A high-gain offset-compensated differential amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohua Fan , Chinmaya Mishra , Edgar Sánchez-Sinencio Single Miller capacitor compensated multistage amplifiers for large capacitive load applications. [Citation Graph (0, 0)][DBLP ] Conf ] Preetam Tadeparthy An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]. [Citation Graph (0, 0)][DBLP ] Conf ] Andre Vilas Boas , Alfredo Olmos A temperature compensated digitally trimmable on-chip IC oscillator with low voltage inhibit capability. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Stefanou , Sameer R. Sonkusale High speed array of oscillator-based truly binary random number generators. [Citation Graph (0, 0)][DBLP ] Conf ] Mourad Oulmane , Gordon W. Roberts A CMOS time amplifier for Femto-second resolution timing measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Jerzy Dabrowski Fault modeling of RF blocks based on noise analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Petraglia , Jorge M. Cañive , Mariane R. Petraglia Accurate fault detection in switched-capacitor filters using structurally allpass building blocks. [Citation Graph (0, 0)][DBLP ] Conf ] David I. Bergman , Bryan C. Waltrip Low thermal error sampling comparator for accurate settling measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Sunwoo Kwon , Franco Maloberti Op-amp swing reduction in sigma-delta modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Liu Wong , Pamela Abshire , Marc H. Cohen Floating gate comparator with automatic offset manipulation functionality. [Citation Graph (0, 0)][DBLP ] Conf ] Masaru Chibashi , Keisuke Eguchi , Takao Waho A novel delta-sigma modulator using resonant-tunneling quantizers. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro M. Figueiredo , João C. Vital Low kickback noise techniques for CMOS latched comparators. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Wei Lin , Yen-Zen Liu , Klaus Y. J. Hsu A low distortion and fast settling automatic gain control amplifier in CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Xian Ping Fan , Pak Kwong Chan A CMOS high-speed multistage preamplifier for comparator design. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw Szczepanski , Slawomir Koziel , Edgar Sánchez-Sinencio Linearized CMOS OTA using active-error feedforward technique. [Citation Graph (0, 0)][DBLP ] Conf ] Nima Maghari , Mohammad Yavari , Omid Shoaei An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Gonggui Xu , Haydar Bilhan A programmable gain amplifier buffer design for video applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Che Wei , Ro-Min Weng , Kun-Yi Lin A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications. [Citation Graph (0, 0)][DBLP ] Conf ] Vojkan Vidojkovic , Johan van der Tang , Eric Hanssen , Arjan J. Leeuwenburgh , Arthur H. M. van Roermund Fully-integrated DECT/Bluetooth multi-band LNA in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Vojkan Vidojkovic , Johan van der Tang , Eric Hanssen , Arjan J. Leeuwenburgh , Arthur H. M. van Roermund Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Vojkan Vidojkovic , Johan van der Tang , Eric Hanssen , Arjan J. Leeuwenburgh , Arthur H. M. van Roermund A DECT/Bluetooth multi-standard front-end with adaptive image rejection in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Khurram Muhammad , Robert B. Staszewski Direct RF sampling mixer with recursive filtering in charge domain. [Citation Graph (0, 0)][DBLP ] Conf ] Rahmi Hezar , Oguz Altun A novel single amplifier architecture for second order noise shaping. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Xu , Jiren Yuan A programmable analog-to-digital converter. [Citation Graph (0, 0)][DBLP ] Conf ] Min Gyu Kim , Gil-Cho Ahn , Un-Ku Moon An improved algorithmic ADC clocking scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Vogel , Gernot Kubin Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Masaaki Naka , Toshimichi Saito Multi-step analog-to-digital converters with trapping window. [Citation Graph (0, 0)][DBLP ] Conf ] Yin-Lung Lu , Yi-Cheng Wu , Kyung-Wan Yu , Wei-Li Chen , M. Frank Chang Design of a 1.8 V 4.9 ~ 5.9 GHz CMOS broadband low noise amplifier with 0.28 dB gain flatness using AMER inductor loads. [Citation Graph (0, 0)][DBLP ] Conf ] Ertan Zencir , Ahmet Tekin , Numan Sadi Dogan , Ercument Arvas A low-power DC-7-GHz SOI CMOS distributed amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] M. Reza Samadi , Aydin I. Karsilayan , José Silva-Martínez Bandwidth enhancement of multi-stage amplifiers using active feedback. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad Yazdi , Payam Heydari A novel non-uniform distributed amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Ziad El-Khatib , Leonard MacEachern , Samy A. Mahmoud A 0.1-12 GHz fully differential CMOS distributed amplifier employing a feedforward distortion cancellation technique. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Cusinato , Stefano Cipriani , Guglielmo Sirna , Gianni Puccio , Eric Duvivier Gain/bandwidth programmable PA control loop for GMS/GPRS quad-band applications. [Citation Graph (0, 0)][DBLP ] Conf ] Suhas Kulhalli , Sumantra Seth , Shih-Tsang Fu An integrated linear RF power detector. [Citation Graph (0, 0)][DBLP ] Conf ] João Ramos , Kenneth Francken , Georges G. E. Gielen , Michiel Steyaert Knowledge- and optimization-based design of RF power amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Jaakko Ketola , Johan Sommarek , Jouko Vankka , Kari Halonen Transmitter utilising bandpass delta-sigma modulator and switching mode power amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Dusan M. Milosevic , Johan van der Tang , Arthur H. M. van Roermund Intermodulation products in the EER technique applied to class-E amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Josias O. Mainardi , Adão Antônio de Souza Jr. , Luigi Carro , Altamiro Amadeu Susin A comparison of totally digital ADCs for SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongjun Yu , Degang Chen , Randall L. Geiger Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations. [Citation Graph (0, 0)][DBLP ] Conf ] Vincenzo Ferragina , Andrea Fornasari , Umberto Gatti , Piero Malcovati , Franco Maloberti , Luigi Marco , Athos Monfasani Use of dynamic element matching in a multi-path sigma-delta modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Nordick , Craig Petrie , Yongjie Cheng Dynamic element matching techniques for delta-sigma ADCs with large internal quantizers. [Citation Graph (0, 0)][DBLP ] Conf ] Mikael Gustavsson , Nianxiong Nick Tan Decimating SC filter for high speed sigma-delta D/A converters. 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