Conferences in DBLP
Deepa Kundur , Yang Zhao , Patrizio Campisi A stenographic framework for dual authentication and compression of high resolution imagery. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Lee , Ling Guan Content-based image retrieval with automated relevance feedback over distributed peer-to-peer network. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Kushki , Panagiotis Androutsos , Konstantinos N. Plataniotis , Anastasios N. Venetsanopoulos A unified framework for similarity calculation between images. [Citation Graph (0, 0)][DBLP ] Conf ] Bong-Ho Lee , So Ra Park , Young Kwon Hahm , Soo In Lee An efficient transmission framework of digital multimedia broadcasting (DMB) systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Liu , Jenq-Neng Hwang A scalable video transmission system using bandwidth inference in congestion control. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Sun Fu , Oscar C. Au Correlation-based watermarking for halftone images. [Citation Graph (0, 0)][DBLP ] Conf ] Yanmei Fang , Jiwu Huang , Shaoquan Wu CDMA-based watermarking resisting to cropping. [Citation Graph (0, 0)][DBLP ] Conf ] Guorong Xuan , Yun Q. Shi , Zhicheng Ni , Jidong Chen , Chengyun Yang , Yizhan Zhen , Junxiang Zheng High capacity lossless data hiding based on integer wavelet transform. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Q. Shi , Zhicheng Ni , Dekun Zou , Changyin Liang , Guorong Xuan Lossless data hiding: fundamentals, algorithms and applications. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony T. S. Ho , Niladri B. Puhan , Pina Marziliano , Anamitra Makur , Yong Liang Guan Perception based binary image watermarking. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Jiang , Mingjing Li , HongJiang Zhang , Jie Zhou Relevance feedback using random subspace method. [Citation Graph (0, 0)][DBLP ] Conf ] Tahir Amin , Ling Guan Interactive content-based image retrieval using Laplacian mixture model in the wavelet domain. [Citation Graph (0, 0)][DBLP ] Conf ] Yinqing Zhao , C. C. Jay Kuo Design issues on request migration for video-on-demand services. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Jing , Mingjing Li , HongJiang Zhang , Bo Zhang Keyword propagation for image retrieval. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Hyun Kim , Rae-Hong Park A novel approach to video sequence matching using color and edge features with the modified Hausdorff distance. [Citation Graph (0, 0)][DBLP ] Conf ] Keman Yu , Jiang Li , Shipeng Li A novel approach to real time multimedia forwarding over heterogeneous networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Cheng Wei , Yuh-Chou Tsai , Chia-Wen Lin Prioritized retransmission for error protection of video streaming over WLANs. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi-Wei Gao , Wen-Nung Lie Video error concealment by using Kalman-filtering technique. [Citation Graph (0, 0)][DBLP ] Conf ] Bontae Koo , Jinkyu Kim , Juhyun Lee , Nak-Woong Eum , Jongdae Kim , Hyunmook Cho Channel decoder architecture of OFDM based DMB system. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoan Lu , Thierry Fernaine , Yao Wang Modelling power consumption of a H.263 video encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Gao , Ping Xue , Weisi Lin A new marker-based watershed algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Ho Chen , Chun-Jen Tsai Out-of-loop rate control for video codec hardware/software co-design. [Citation Graph (0, 0)][DBLP ] Conf ] Naoki Nitanda , Miki Haseyama , Hideo Kitajima An audio-scene cut detection method using fuzzy c-means algorithm for audio-visual indexing. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Chieh Chi , Mei-Juan Chen , Ching-Ting Hsu Region-of-Interest video coding by fuzzy control for H.263+ standard. [Citation Graph (0, 0)][DBLP ] Conf ] Ko-Cheung Hui , Wan-Chi Siu , Yui-Lam Chan New adaptive partial distortion search using clustered pixel matching error characteristic. [Citation Graph (0, 0)][DBLP ] Conf ] Shilin L. Wang , Wing Hong Lau , Shu Hung Leung , H. Yan A real-time automatic lipreading system. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Lu , Zhenyan Li , Yap-Peng Tan Model-based video scene clustering with noise analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Guang Dai , Yuntao Qian Face recognition with the robust feature extracted by the generalized Foley-Sammon transform. [Citation Graph (0, 0)][DBLP ] Conf ] Cenk Demiroglu , David V. Anderson Two-sensor noise robust ASR with missing frames for Aurora2 task. [Citation Graph (0, 0)][DBLP ] Conf ] Prem Kuchi , Sethuraman Panchanathan Intrinsic mode functions for gait recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Rastislav Lukac , Konstantinos N. Plataniotis A new CFA interpolation technique for single-sensor digital cameras. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoxiong Hua , Gang Qu QoS-driven scheduling for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson Yen-Chung Chang , Kun-Bin Lee , Chein-Wei Jen Trace-path analysis and performance estimation for multimedia application in embedded system. [Citation Graph (0, 0)][DBLP ] Conf ] Jinghong Zheng , Lap-Pui Chau A temporal error concealment algorithm for H.264 using Lagrange interpolation. [Citation Graph (0, 0)][DBLP ] Conf ] Chang-Hyo Yu , Lee-Sup Kim An adaptive spatial filter for early depth test. [Citation Graph (0, 0)][DBLP ] Conf ] Kuan-Hung Chen , Jiun-In Guo , Jinn-Shyan Wang , Ching-Wei Yeh , Tien-Fu Chen A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Hae-Yong Kang , Kyung-Ah Jeong , Jung-Yang Bae , Young-Su Lee , Seung-Ho Lee MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller. [Citation Graph (0, 0)][DBLP ] Conf ] Yueh-Yi Wang , Yan-Tsung Peng , Chun-Jen Tsai VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders. [Citation Graph (0, 0)][DBLP ] Conf ] Donghyun Kim , Lee-Sup Kim Division-free rasterizer for perspective-correct texture filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Hsun Chen , Oscal T.-C. Chen , Teng-Yi Wang , Chi-Lung Wang An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Peter H. W. Wong , Andy Chang , Oscar C. Au On improving the iterative watermark embedding technique for JPEG-to-JPEG watermarking. [Citation Graph (0, 0)][DBLP ] Conf ] Alexia Giannoula , Dimitrios Hatzinakos Data hiding for multimodal biometric recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Shien Lu On the security of structural information extraction/embedding for images. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Chen , Hongxun Yao , Wen Gao , Shaohui Liu A robust watermarking method based on wavelet and Zernike transform. [Citation Graph (0, 0)][DBLP ] Conf ] Yazhou Liu , Wen Gao , Hongxun Yao , Shaohui Liu A texture-based tamper detection scheme by fragile watermark. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Waqas Bhatti , Yongjin Wang , Ling Guan A neural network approach for human emotion recognition in speech. [Citation Graph (0, 0)][DBLP ] Conf ] Ji Tao , Yap-Peng Tan A probabilistic reasoning approach to closed-room people monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos D. Doulamis , Pavlos S. Georgilakis Adaptive multimedia content personalization. [Citation Graph (0, 0)][DBLP ] Conf ] Naixiang Lian , Yap-Peng Tan Probabilistic approach to K-nearest neighbor video retrieval. [Citation Graph (0, 0)][DBLP ] Conf ] Shi Lu , Michael R. Lyu , Irwin King Video summarization by spatial-temporal graph optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Lihang Ying , Anup Basu , Satish K. Tripathi Multi-server optimal bandwidth monitoring for collaborative distributed retrieval. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wang , Cedric Nishan Canagarajah , David W. Redmill , David R. Bull Multiple description video coding based on zero padding. [Citation Graph (0, 0)][DBLP ] Conf ] Kitae Nahm , C. C. Jay Kuo Low-variance TCP-friendly throughput estimation for congestion control of layered video multicast. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Ting Hsu , Mei-Juan Chen , Chin-Hui Huang High performance spatial-temporal de-interlacing technique using interfield information. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Chen , Tiejun Lv , Haitao Zheng Cross-layer design for QoS wireless communications. [Citation Graph (0, 0)][DBLP ] Conf ] Jui-Cheng Yen , Hun-Chen Chen , Shin-Shian Jou A new cryptographic system and its VLSI implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Bing-Fei Wu , Chung-Fu Lin Analysis and architecture design for high performance JPEG2000 coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Mladen Panovic , Andreas Demosthenous A compact block-matching cell for analogue motion estimation processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yeong-Kang Lai , Lien-Fei Chen A performance-driven configurable motion estimator for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed Sayed , Wael M. Badawy A novel embedded memory architecture for real-time mesh-based motion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Deepak N. Agarwal , Sumitkumar N. Pamnani , Gang Qu , Donald Yeung Transferring performance gain from software prefetching to energy reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Gerosa , Andrea Neviani A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter. [Citation Graph (0, 0)][DBLP ] Conf ] Juang-Ying Chueh , Conrad H. Ziesler , Marios C. Papaefthymiou Empirical evaluation of timing and power in resonant clock distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Chen Tseng , Chien-Ching Lin , Hsie-Chia Chang , Chen-Yi Lee A power and area efficient multi-mode FEC processor. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Willingham , Izzet Kale Asynchronous, quasi-Adiabatic (Asynchrobatic) logic for low-power very wide data width applications. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Onishi , Mitsuo Ikeda , Jiro Naganuma , Makoto Endo , Yoshiyuki Yashima A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. [Citation Graph (0, 0)][DBLP ] Conf ] Faycal Bensaali , Abbes Amira , Ahmed Bouridane An efficient architecture for color space conversion using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Wen Huang , Bing-Yu Hsieh , Tung-Chien Chen , Liang-Gee Chen Hardware architecture design for H.264/AVC intra frame coder. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chien Chen , Yu-Wen Huang , Liang-Gee Chen Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Saas , Artur Wróblewski , Josef A. Nossek Low-power DA-converters for display applications using stepwise charging and charge recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Eriksson , Per Larsson-Edefors Glitch-conscious low-power design of arithmetic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyuki Yamanaka , Vasily G. Moshnyaga Reducing multiplier energy by data-driven voltage variation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael M. Yang , James A. Barby A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Wei Chen , Wen-Cheng Yen A low power and fast wake up circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Hafijur Rahman , Chaitali Chakrabarti A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Yeh Chen , Shao-Yi Chien , Wei-Min Chao , Yu-Wen Huang , Liang-Gee Chen Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile. [Citation Graph (0, 0)][DBLP ] Conf ] Kun-Bin Lee , Hao-Yun Chin , Hui-Cheng Hsu , Chein-Wei Jen QME: an efficient subsampling-based block matching algorithm for motion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Basu , Ashis Kumar Mal , Anindya Sundar Dhar Digital controlled analog architecture for DCT and DST using capacitor switching. [Citation Graph (0, 0)][DBLP ] Conf ] Siou-Shen Lin , Po-Chih Tseng , Liang-Gee Chen Low-power parallel tree architecture for full search block-matching motion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Kun-Bin Lee , Jih-Yiing Lin , Chein-Wei Jen A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. [Citation Graph (0, 0)][DBLP ] Conf ] Siu-Kei Wong , Chi-Ying Tsui Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail Low power coupling-based encoding for on-chip buses. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Fu Chen , Tsung-Ming Hsieh , Chun-Li Wei Unified bus encoding by stream reconstruction with variable strides. [Citation Graph (0, 0)][DBLP ] Conf ] Abdullah Mamun , Rajendra S. Katti A new parallel architecture for low power linear feedback shift registers. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Hung Liu , Bai-Jue Shieh , Chen-Yi Lee A low-power group-based VLD design. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Lin Chang , Shyh-Feng Lin , Liang-Gee Chen Extended intelligent edge-based line average with its implementation and test method. [Citation Graph (0, 0)][DBLP ] Conf ] Amine Bermak , Farid Boussaïd , Abdesselam Bouzerdoum A low power current-mode pixel with on-chip FPN cancellation and digital shutter. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Yamasaki , Tadashi Shibata A real-time VLSI median filter employing two-dimensional bit-propagating architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Po-Chih Tseng , Chao-Tsung Huang , Liang-Gee Chen Reconfigurable discrete cosine transform processor for object-based video signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Simon , Matthias Müller , Holger Gryska , Andreas Wortmann , Steffen Buch An instruction set for the efficient implementation of the CORDIC algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Kimish Patel , Enrico Macii , Massimo Poncino Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendra Katti , Xiaoyu Ruan Left-to-right binary signed-digit recoding for elliptic curve cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Yuejian Wu Low power decoding of BCH codes. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Md. Rafiqul Islam , Rumana Nazmul , Md. Anwarul Haque , Ahsan Raja Chowdhury A heuristic approach to synthesize Boolean functions using TANT network. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Steinert , Stefano Marsili Power consumption optimization for low latency Viterbi Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Hyun-Yong Lee , In-Cheol Park A fast Reed-Solomon Product-Code decoder without redundant computations. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Dae Kim , Sug Hyun Jeong , Myung Hoon Sunwoo , Kyung Ho Kim Novel bit manipulation unit for communication digital signal processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Zhong , Tong Zhang Joint code-encoder-decoder design for LDPC coding system VLSI implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Hsie-Chia Chang , Chien-Ching Lin , Tien-Yuan Hsiao , Jieh-Tsorng Wu , Ta-Hui Wang Multi-level memory systems using error control codes. [Citation Graph (0, 0)][DBLP ] Conf ] Se-Hyeon Kang , In-Cheol Park Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. [Citation Graph (0, 0)][DBLP ] Conf ] Jinn-Shyan Wang , Shang-Jyh Shieh , Ching-Wei Yeh , Yuan-Hsun Yeh Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. [Citation Graph (0, 0)][DBLP ] Conf ] Masaaki Iijima , Katsuya Fujita , Kazuki Fukuoka , Masahiro Numa , Keisuke Yamamoto , Kengo Takata A technique for high-speed circuits on SOI using look-ahead type active body bias control. [Citation Graph (0, 0)][DBLP ] Conf ] Baohua Wang , Pinaki Mazumder Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials. [Citation Graph (0, 0)][DBLP ] Conf ] Walid Elgharbawy , Magdy A. Bayoumi B-DTNMOS: a novel bulk dynamic threshold NMOS scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Volkan Kursun , Eby G. Friedman Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Layer , Hans-Jörg Pfleiderer , Christoph Heer A scalable compact architecture for the computation of integer binary logarithms through linear approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Magnus Karlsson , Mark Vesterbacka , Wlodek Kulesza A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoqiang Bi , Wei Wang , Asim J. Al-Khalili Modulo deflation in (2n +1, 2n , 2n -1) converters. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Arnold Geometric-mean interpolation for logarithmic number systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kwen-Siong Chong , Bah-Hwee Gwee , Joseph Sylvester Chang A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Aydin O. Balkan , Gang Qu , Uzi Vishkin Arbitrate-and-move primitives for high throughput on-chip interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Marcin Jeske , Grzegorz Blakiewicz , Malgorzata Chrzanowska-Jeske , Benyi Wang Substrate noise-aware floorplanning for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Bhutoria , Chaitali Chakrabarti Parameterized SoC design for portable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Taek-Jun Kwon , Joong-Seok Moon , Jeff Sondeen , Jeffrey T. Draper A 0.18 µm implementation of a floating-point unit for a processing-in-memory system. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksandar Pance , Madan Mohan , Paul Master Power-aware implementation of ASIC/SOC in 0.13 micron CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Eriksson , Per Larsson-Edefors Dynamic pass-transistor dot operators for efficient parallel-prefix adders. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Gaetano Palumbo , Massimo Poli A gate-level strategy to design Carry Select Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Kenny Johansson , Oscar Gustafsson , Lars Wanhammar Switching activity in bit-serial constant-coefficient multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar Gustafsson , Andrew G. Dempster , Lars Wanhammar Multiplier blocks using carry-save adders. [Citation Graph (0, 0)][DBLP ] Conf ] Ramyanshu Datta , Jacob A. Abraham , Robert K. Montoye , Wendy Belluomini , Hung Ngo , Chandler McDowell , Jente B. Kuang , Kevin J. Nowka A low latency and low power dynamic Carry Save Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar F. M. Albuquerque , Manuel M. Silva An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Husni M. Habal , Terri S. Fiez , Kartikeya Mayaram An accurate and efficient estimation of switching noise in synchronous digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando Mendoza-Hernandez , Mónico Linares Aranda , Víctor H. Champac Vilela An improved technique to increase noise-tolerance in dynamic digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando Mendoza-Hernandez , Mónico Linares Aranda , Víctor H. Champac Vilela The noise immunity of dynamic digital circuits with technology scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Omar Hafiz , Pinhong Chen , Janet Wang A new non-iterative model for switching window computation with crosstalk noise. [Citation Graph (0, 0)][DBLP ] Conf ] Keshab K. Parhi Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Ruwan Ratnayake , Gu-Yeon Wei , Aleksandar Kavcic Pipelined parallel architecture for high throughput MAP detectors. [Citation Graph (0, 0)][DBLP ] Conf ] Yuping Zhang , Keshab K. Parhi Parallel Turbo decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Ming Wu , Ming-Der Shieh , Chien-Hsing Wu , Yin-Tsung Hwang , Jun-Hong Chen , Hsin-Fu Lo VLSI architecture exploration for sliding-window Log-MAP decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Wing-Kin Chan , Chiu-sing Choy , Cheong-fat Chan , Kong-Pang Pun An asynchronous SOVA decoder for wireless communication application. [Citation Graph (0, 0)][DBLP ] Conf ] Junmou Zhang , Eby G. Friedman Decoupling technique and crosstalk analysis for coupled RLC interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail Effect of relative delay on the dissipated energy in coupled interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Junmou Zhang , Eby G. Friedman Effect of shield insertion on reducing crosstalk noise between coupled interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Pappu , Alyssa B. Apsel Electrical isolation and fanout in intra-chip optical interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Bassel Soudan Managing inductive coupling in wide signal busses. [Citation Graph (0, 0)][DBLP ] Conf ] Refik Sever , A. Neslin Ismailoglu , Yusuf Çagatay Tekmen , Murat Askar A high speed ASIC implementation of the Rijndael algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Pionteck , Thorsten Staake , Thomas Stiefmeier , Lukusa D. Kabulepa , Manfred Glesner Design of a reconfigurable AES encryption/decryption engine for mobile terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Paris Kitsos , Michalis D. Galanis , Odysseas G. Koufopavlou High-speed hardware implementations of the KASUMI block cipher. [Citation Graph (0, 0)][DBLP ] Conf ] Nick A. Moldovyan , Ma A. Eremeev , Nicolas Sklavos , Odysseas G. Koufopavlou New class of the FPGA efficient cryptographic primitives. [Citation Graph (0, 0)][DBLP ] Conf ] Soner Yesil , A. Neslin Ismailoglu , Yusuf Çagatay Tekmen , Murat Askar Two fast RSA implementations using high-radix montgomery algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon Allan , John Knight Low complexity digital PLL for instant acquisition CDR. [Citation Graph (0, 0)][DBLP ] Conf ] Amer H. Atrash , Brian Butka A technique to deskew differential PCB traces. [Citation Graph (0, 0)][DBLP ] Conf ] Xiong Liu , Alan N. Willson Jr. A new interpolated symbol timing recovery method. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Lun Chen , Ming-Dou Ker A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals. [Citation Graph (0, 0)][DBLP ] Conf ] Che-Hao Chuang , Ming-Dou Ker Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Wim J. C. Melis , Peter Y. K. Cheung , Wayne Luk Autonomous Memory Block for reconfigurable computing. [Citation Graph (0, 0)][DBLP ] Conf ] Volnei A. Pedroni Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Tyson S. Hall , Christopher M. Twigg , Paul E. Hasler , David V. Anderson Application performance of elements in a floating-gate FPAA. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Yung Hsiao , Chun-Ho Hua , Chien-Chen Lin A novel FPGA architectural implementation of pipelined thinning algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Shuenn-Shyang Wang , Wan-Sheng Ni An efficient FPGA implementation of advanced encryption standard algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy A. El-Moursy , Eby G. Friedman Exponentially tapered H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP ] Conf ] Behzad Mesgarzadeh , Christer Svensson , Atila Alvandpour A new mesochronous clocking scheme for synchronization in SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Müller , Andreas Wortmann , Sven Simon , Michael Kugel , Tim Schoenauer The impact of clock gating schemes on the power dissipation of synthesizable register files. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuki Fukuoka , Masaaki Iijima , Kenji Hamada , Masahiro Numa , Akira Tada Leakage power reduction for clock gating scheme on PD-SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Baris Taskin , Ivan S. Kourtev Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Chih Hsieh , Zheng-Hong Wang , Hongchin Lin , Yen-Tai Lin A new dual pumping circuit without body effects for low supply voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinando Bedeschi , Edoardo Bonizzoni , Osama Khouri , Claudio Resta , Guido Torelli A fully symmetrical sense amplifier for non-volatile memories. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hsing Cheng , Chia-Hung Wei , Shu-Yu Jiang Static divided word matching line for low-power Content Addressable Memory design. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin Mohan , Manoj Sachdev Low power dual matchline ternary content addressable memory. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Labbé , Annie Pérez , Jean Michel Portal Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Ada Fort , Luca Pancioni , Santina Rocchi , Valerio Vignoli Positive-Feedback Source-Coupled Logic: a delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Tin Wai Kwan , Maitham Shams Multi-GHz energy-efficient asynchronous pipelined circuits in MOS Current Mode Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Avni Morgul , Turgay Temel A new level restoration circuit for multi-valued logic. [Citation Graph (0, 0)][DBLP ] Conf ] Shahnam Khabiri , Maitham Shams Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Cabrini , Rino Micheloni , Osama Khouri , Stefano Gregori , Guido Torelli High input range sense comparator for multilevel Flash memories. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Mahmoodi-Meimand , Kaushik Roy Dual-edge triggered level converting flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Yin Sung , Robert C. Chang A novel CMOS double-edge triggered flip-flop for low-power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Peiyi Zhao , Golconda Pradeep Kumar , Magdy Bayoumi Contention reduced/conditional discharge flip-flops for level conversion in CVS systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arkadiy Morgenshtein , Alexander Fish , Israel A. Wagner An efficient implementation of D-Flip-Flop using the GDI technique. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Mahmoodi-Meimand , Kaushik Roy Data-retention flip-flops for power-down applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad H. Tehranipour , Mehrdad Nourani , Karim Arabi , Ali Afzali-Kusha Mixed RL-Huffman encoding for power reduction and data compression in scan test. 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