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IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2002 (conf/iscas/2002-4)

  1. Peyman Arian, Tapio Saramäki, S. K. Mitra
    A systematic technique for optimizing multiple branch FIR filters for sampling rate conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:1-4 [Conf]
  2. Djordje Babic, J. Vesma, Tapio Saramäki, Markku Renfors
    Implementation of the transposed Farrow structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:5-8 [Conf]
  3. Bojan Vrcelj, P. P. Vaidyanathan
    Fractional biorthogonal partners and application in signal interpolation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:9-12 [Conf]
  4. P. M. Yiu, S. C. Chan
    Multiplier-less implementation of linear phase cosine modulated filter banks with composite channel number. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:13-16 [Conf]
  5. David B. H. Tay
    Lifting based integer wavelet transform with binary coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:17-20 [Conf]
  6. T. Gawa, K. Taniguchi
    A 50% duty-cycle correction circuit for PLL output. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:21-24 [Conf]
  7. R. Strandberg, P. Andreani, L. Sundstrom
    Bandwidth considerations for a CALLUM transmitter architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:25-28 [Conf]
  8. T. H. Huang, Ertan Zencir, Numan Sadi Dogan, Andrea Arvas
    A 22-mW 435-MHz differential CMOS high-gain LNA for subsampling receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:29-32 [Conf]
  9. Ertan Zencir, Numan Sadi Dogan, Ercument Arvas
    A 10-mW 435-MHz differential CMOS LNA for low-IF receivers in space applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:33-36 [Conf]
  10. Nicola Massari, Lorenzo Gonzo, Massimo Gottardi, Andrea Simoni
    A monolithic low power pulsed optical encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:37-40 [Conf]
  11. I. Hehemann, W. Brockherde, A. Bussmann, H. Hofmann, A. Kemna, R. Kokozinski, H. Richter, Bedrich J. Hosticka
    A new detector architecture for optical pickup units in DVD systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:41-44 [Conf]
  12. Guangbin Zhang, Jin Liu
    A robust edge detector for motion detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:45-48 [Conf]
  13. Hwang-Cherng Chow, Yung-Kuo Ho
    New pixel-shared design and split-path readout of CMOS image sensor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:49-52 [Conf]
  14. Amine Bermak
    A CMOS imager with PFM/PWM based analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:53-56 [Conf]
  15. A. H. Titus, A. Gopalan
    A differential summing amplifier for analog VLSI systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:57-60 [Conf]
  16. Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen
    Parameter optimization tool for enhancing on-chip network performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:61-64 [Conf]
  17. Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler
    Switching activity estimation of finite state machines for low power synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:65-68 [Conf]
  18. Jacqueline E. Rice, Jon C. Muzio
    Antisymmetries in the realization of Boolean functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:69-72 [Conf]
  19. Jaewon Seo, Taewhan Kim
    Memory exploration utilizing scheduling effects in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:73-76 [Conf]
  20. J. A. Lopez, G. Domenech, R. Ruiz, Tom J. Kazmierski
    Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:77-80 [Conf]
  21. Chi Ta Wu, TingTing Hwang
    Instruction buffering for nested loops in low power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:81-84 [Conf]
  22. Gaetano Palumbo, F. Pappalardo, S. Sannella
    Evaluation on power reduction applying gated clock approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:85-88 [Conf]
  23. Matthias Müller, Andreas Wortmann, Sven Simon, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek
    Low power register file architecture for application specific DSPs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:89-92 [Conf]
  24. Nan-Ying Shen, Oscal T.-C. Chen
    Low-power multipliers by minimizing switching activities of partial products. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:93-96 [Conf]
  25. G. Sinevriotis, Thanos Stouraitis
    A novel list-scheduling algorithm for the low-energy program execution. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:97-100 [Conf]
  26. Seyed Reza Abdollahi, S. Kiaei, B. Bakkaloglu, Seid Mehdi Fakhraie, R. Anvari, S. E. Abdollahi
    An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:101-104 [Conf]
  27. Jouko Vankka, Jonne Lindeberg, Kari Halonen
    FIR filters for compensating D/A converter frequency response distortion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:105-108 [Conf]
  28. Ediz Çetin, Izzet Kale, Richard C. S. Morling
    Correction of transmitter gain and phase errors at the receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:109-112 [Conf]
  29. Min-Yi Wang, R. R.-B. Sheen, Oscal T.-C. Chen, R. Y. J. Tsen
    A dual-band RF front-end for WCDMA and GPS applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:113-116 [Conf]
  30. Jussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, A. Parssinen, Kari Halonen
    RF gain control in direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:117-120 [Conf]
  31. Jui-Cheng Yen, Jiun-In Guo
    Design of a new signal security system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:121-124 [Conf]
  32. V. Krishnan, Wasfy B. Mikhael
    A novel adaptive algorithm applied to a class of redundant representation vector quantizers for waveform and model based coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:125-128 [Conf]
  33. T. Miura, Y. Fujishiro
    Spectrum management of pulse transmission by high-cut filter line. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:129-132 [Conf]
  34. Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee
    A high throughput context-based adaptive arithmetic codec for JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:133-136 [Conf]
  35. Man Guo, M. Omair Ahmad, M. N. S. Swamy, Chunyan Wang
    An adaptive Viterbi algorithm based on strongly connected trellis decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:137-140 [Conf]
  36. R. Venkatesh Babu, K. R. Ramakrishnan
    Content-based video retrieval using motion descriptors extracted from compressed domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:141-144 [Conf]
  37. Feng Jing, Mingjing Li, HongJiang Zhang, Bo Zhang
    Region-based relevance feedback in image retrieval. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:145-148 [Conf]
  38. T. M. Liu, H. J. Zhang, F. H. Qi
    A novel video key frame extraction algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:149-152 [Conf]
  39. Gamal Fahmy, Sethuraman Panchanathan
    A lifting based system for optimal compression and classification in the JPEG2000 framework. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:153-156 [Conf]
  40. Wen-Nung Lie, Wen-Hung Peng, Cheng-Hung Chuang
    Efficient content-based CT brain image retrieval by using region shape features. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:157-160 [Conf]
  41. Dávid Bálya, Csaba Rekeczky, Tamás Roska
    A realistic mammalian retinal model implemented on complex cell CNN universal machine. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:161-164 [Conf]
  42. Paolo Arena, Holk Cruse, Luigi Fortuna, Mattia Frasca, Luca Patané
    A cellular nonlinear approach to decentralized locomotion control of the stick insect. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:165-168 [Conf]
  43. S. Purushothaman, Christofer Toumazou, Julius Georgiou
    Towards fast solid state DNA sequencing. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:169-172 [Conf]
  44. D. R. Kipke, D. S. Pellinen, R. J. Vetter
    Advanced neural implants using thin-film polymers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:173-176 [Conf]
  45. Ronald Tetzlaff, D. Weiss
    Cellular neural networks for the anticipation of epileptic seizures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:177-180 [Conf]
  46. Radu M. Secareanu, Bill Peterson, D. Hartman
    A low-voltage low-noise digital buffer system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:181-184 [Conf]
  47. Fernando Mendoza-Hernandez, M. Linares, Víctor H. Champac, A. Diaz-Sanchez
    A new technique for noise-tolerant pipelined dynamic digital circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:185-188 [Conf]
  48. Qinwei Xu, Pinaki Mazumder, Li Ding 0002
    Novel macromodeling for on-chip RC/RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:189-192 [Conf]
  49. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Optimising bandwidth over deep sub-micron interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:193-196 [Conf]
  50. Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:197-200 [Conf]
  51. Ming-Hsiu Lai, Ming-Feng Yu, Sau-Gee Chen
    An efficient modified Phong shading algorithm & its low-complexity realization. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:201-204 [Conf]
  52. Fan Xu, Guichang Zhong, D. D. Richard III, Alan N. Willson Jr.
    A ring-processor based blind beamformer design for use in wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:205-208 [Conf]
  53. Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu
    A scalable sorting architecture based on maskable WTA/MAX circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:209-212 [Conf]
  54. Meng-Da Yang, An-Yeu Wu
    A new pipelined adaptive DFE architecture with improved convergence rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:213-216 [Conf]
  55. Chi-Sheng Lin, Bin-Da Liu
    Design of a pipelined and expandable sorting architecture with simple control scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:217-220 [Conf]
  56. Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan, José E. Franca
    A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:221-224 [Conf]
  57. Maurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers
    Multirate cascaded continuous time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:225-228 [Conf]
  58. Hassan Aboushady, Marie-Minerve Louërat
    Systematic approach for discrete-time to continuous-time transformation of Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:229-232 [Conf]
  59. Friedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli
    Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:233-236 [Conf]
  60. Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen
    Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:237-240 [Conf]
  61. Drazen Jurisic, George S. Moschytz, Neven Mijat
    Low-sensitivity active-RC high- and band-pass second-order Sallen & Key allpole filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:241-244 [Conf]
  62. Yigang He, Jinguang Jiang, Yichuang Sun
    CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:245-248 [Conf]
  63. A. Hassan, K. Sharaf, H. El-Ghitani, H. F. Ragaie
    A new low power transconductor for Gm-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:249-252 [Conf]
  64. J. Lee, Khaled Hayatleh, F. J. Lidgey, J. Drew
    Tuneable linear transconductance cell for Gm-C filter applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:253-256 [Conf]
  65. Saeid Mehrmanesh, Seyed Mojtaba Atarodi
    A high dynamic range CMOS variable gain filter for ADSL. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:257-260 [Conf]
  66. J. A. Bragg, Edgar A. Brown, Paul E. Hasler, Stephen P. DeWeerth
    A silicon model of an adapting motoneuron. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:261-264 [Conf]
  67. Kee-Chee Tiew, J. Cusey, Randall L. Geiger
    A curvature compensation technique for bandgap voltage references using adaptive reference temperature. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:265-268 [Conf]
  68. Anthony Chan Carusone, David A. Johns
    Analog filter adaptation using a dithered linear search algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:269-272 [Conf]
  69. N. Prasad, H. Dinc, Aydin I. Karsilayan
    An adaptive analog video line driver with impedance matching based on peak detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:273-276 [Conf]
  70. Xiaohong Sun, K. R. Laker
    Tonal behavior analysis of an adaptive second-order sigma-delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:277-280 [Conf]
  71. Paolo Arena, Claudia Bonomo, Luigi Fortuna, Mattia Frasca
    Electro-active polymers as CNN actuators for locomotion control. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:281-284 [Conf]
  72. Salvatore Baglio, Salvatore Castorina, Luigi Fortuna, Nicolò Savalli
    Development of autonomous, mobile micro-electro-mechanical devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:285-288 [Conf]
  73. D. W. Fogliatti
    Interconnected resonant gyros for improved performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:289-292 [Conf]
  74. Juan A. Acebrón, Adi R. Bulsara, W.-J. Rappel
    Noise-mediated cooperative behavior in a system of coupled DC SQUIDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:293-296 [Conf]
  75. Luigi Occhipinti, Luigi Fortuna
    Organic molecules and composites with applications in micro and nanoelectronic systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:297-300 [Conf]
  76. Joseph D. Neff, Brian K. Meadows, Edgar A. Brown, Stephen P. DeWeerth, Paul E. Hasler
    A CMOS coupled nonlinear oscillator array. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:301-304 [Conf]
  77. Mandana Amiri, Andreas G. Veneris, Ivor Ting
    Design rewiring for power minimization [logic design]. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:305-308 [Conf]
  78. Payam Heydari
    Energy dissipation modeling of lossy transmission lines driven by CMOS inverters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:309-312 [Conf]
  79. Athanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis
    Confronting violations of the TSCG(T) in low-power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:313-316 [Conf]
  80. O. Wing, Tan Jun, Jin-mei Lai, Junyan Ren, Qianling Zhang
    Iterative solution of ODE-PDE-AE systems for RF circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:317-320 [Conf]
  81. Yoonseo Choi, Taewhan Kim
    An efficient low-power binding algorithm in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:321-324 [Conf]
  82. S. Ramamurthy, S. Madhavankutty, V. Meena, R. Gupta
    JPEG-2000 on an advanced architecture, multiple execution unit DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:325-328 [Conf]
  83. Hong-Hui Chen, Chung-Jr Lian, Te-Hao Chang, Liang-Gee Chen
    Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:329-332 [Conf]
  84. Takahiko Masuzaki, Hiroshi Tsutsui, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    JPEG2000 adaptive rate control for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:333-336 [Conf]
  85. C. Duanmu, M. Omair Ahmad, M. N. S. Swamy, Ali Shatnawi
    A vector based fast block motion estimation algorithm for implementation on SIMD architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:337-340 [Conf]
  86. Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen
    A hardware accelerator for video segmentation using programmable morphology PE array. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:341-344 [Conf]
  87. Tanes Tanitteerapan, S. Mori
    Simplified input current waveshaping technique by using inductor voltage sensing for power factor correction isolated Sepic rectifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:345-348 [Conf]
  88. M. Ponce, A. J. Martinez, J. Correa, J. Arau
    Evaluation of an improved input current shaper used as power factor corrector in electronic ballast. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:349-352 [Conf]
  89. Bor-Ren Lin, Tsung-Liang Hung
    A single-phase three-level boost type rectifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:353-356 [Conf]
  90. R. Ramos, Domingo Biel, Francesc Guinjoan, E. Fossas
    Design considerations in sliding-mode controlled parallel-connected inverters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:357-360 [Conf]
  91. Tadashi Suetsugu, Marian K. Kazimierczuk
    Voltage-clamped class E amplifier with a Zener diode across the switch. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:361-364 [Conf]
  92. Xiaojuan Hu, Linda DeBrunner, Victor E. DeBrunner
    An efficient design for FIR filters with variable precision. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:365-368 [Conf]
  93. Sungwook Kim, Gerald E. Sobelman
    Efficient digit-serial FIR filters with skew-tolerant domino. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:369-372 [Conf]
  94. Tughrul Arslan, Ahmet T. Erdogan
    Low power implementation of high throughput FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:373-376 [Conf]
  95. K. Lasanen, Elvi Räisänen-Ruotsalainen, Juha Kostamovaara
    A 1-V, self adjusting, 5-MHz CMOS RC-oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:377-380 [Conf]
  96. Y. Cheng, Krzysztof Czuba, G. Kompa
    K-band phase locked hair-pin oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:381-384 [Conf]
  97. Honghao Ji, R. W. Newcomb
    A structurally stable realization for Jacobi elliptic functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:385-388 [Conf]
  98. Lixin Yang, Yijun Zhou, Jiren Yuan
    A non-feedback multiphase clock generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:389-392 [Conf]
  99. N. Barton, D. Ozis, Terri S. Fiez, Kartikeya Mayaram
    Analysis of jitter in ring oscillators due to deterministic noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:393-396 [Conf]
  100. F. Dulger, E. Sanchez-Sinencio
    Design trade-offs of a symmetric linearized CMOS LC VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:397-400 [Conf]
  101. R. R.-B. Sheen, Oscal T.-C. Chen, Zheng-Dao Lee
    A high-performance CMOS multiphase voltage-controlled oscillator for communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:401-404 [Conf]
  102. M. Nakamura, T. Matsuoka, K. Taniguchi
    CMOS phase-shift VCO for short-range wireless communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:405-408 [Conf]
  103. N. Seshan, J. Rajagopalan, Kartikeya Mayaram
    Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:409-412 [Conf]
  104. G. Ritzberger, J. Bock, H. Knapp, L. Treitinger, Arpad L. Scholtz
    38 GHz low-power static frequency divider in SiGe bipolar technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:413-416 [Conf]
  105. David B. H. Tay, Saman S. Abeysekera
    Design of variable Laguerre filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:417-420 [Conf]
  106. Chien-Cheng Tseng
    Design of variable fractional delay FIR filter using differentiator bank. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:421-424 [Conf]
  107. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
    Design and implementation of a novel algorithm for general purpose median filtering on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:425-428 [Conf]
  108. Jean-Jacques Fuchs, Bernard Delyon
    Min-max interpolators and Lagrange interpolation formula. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:429-432 [Conf]
  109. Richard C. S. Morling, Izzet Kale
    Dynamic range of allpass filter structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:433-436 [Conf]
  110. Sangwook Kim, E. Greeneich
    Body effect compensated switch for low voltage switched-capacitor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:437-440 [Conf]
  111. Seng-Pan U., Rui Paulo Martins, José E. Franca
    Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:441-444 [Conf]
  112. Omid Oliaei
    Noise analysis of correlated double sampling SC-integrators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:445-448 [Conf]
  113. Jozef Adut, José Silva-Martínez
    A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:449-452 [Conf]
  114. Apisak Worapishet, R. Sitdhikorn, John B. Hughes
    Low-power complex channel filtering using cascoded class AB switched-currents. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:453-456 [Conf]
  115. D. Takafuji, S. Taoka, T. Watanabe
    Efficient approximation algorithms for the maximum weight matching problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:457-460 [Conf]
  116. S. Kawarai
    Exact discretization of differential equations by s-z transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:461-464 [Conf]
  117. Alexander Zemliak
    On start point selection for the time-optimal system design algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:465-468 [Conf]
  118. Arasch Honarbacht, Fritz Boschen, Anton Kummert, N. Harle
    Synchronization of distributed simulations-a Kalman filter approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:469-472 [Conf]
  119. Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen
    Interconnection of autonomous error-tolerant cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:473-476 [Conf]
  120. Salvatore Pontarelli, Gian-Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano
    A self-checking cell logic block for fault tolerant FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:477-480 [Conf]
  121. Jie Dai, C. J. Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel
    Cell library for automatic synthesis of analog error control decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:481-484 [Conf]
  122. Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen
    Interconnect peak current reduction for wavelet array processor using self-timed signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:485-488 [Conf]
  123. A. Anttonen, T. Rautio
    Performance and complexity analysis for adaptive sample rate converters in GSM/UMTS/HIPERLAN2 mobile transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:489-492 [Conf]
  124. M. C. Sun, Daniel P. K. Lun
    Power-line communications using DWMT modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:493-496 [Conf]
  125. Cheong Yiu Fung, S. C. Chan
    Estimation of fast fading channel in impulse noise environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:497-500 [Conf]
  126. Chung-Yao Chang, Shiunn-Jang Chern
    The norm constraint IQML beamforming algorithm for wideband and coherent jammers suppression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:501-504 [Conf]
  127. F. R. Palomo, J. M. Quero, Leopoldo García Franquelo
    Intermodulation distortion measures in a stochastic resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:505-508 [Conf]
  128. Lige Wang, M. N. El-Gamal
    A CMOS companding-based third order Chebyshev filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:509-512 [Conf]
  129. A. E. Hussein, Mohamed I. Elmasry
    Fractional-N frequency synthesizer for wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:513-516 [Conf]
  130. Chris van den Bos, Chris J. M. Verhoeven
    Frequency division using an injection-locked relaxation oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:517-520 [Conf]
  131. Robert J. Marks II, B. Thompson, Mohamed A. El-Sharkawi, Warren L. J. Fox, Robert T. Miyamoto
    Stochastic resonance of a threshold detector: image visualization and explanation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:521-523 [Conf]
  132. Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao
    An embedded DSP core for wireless communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:524-527 [Conf]
  133. Karen O. Egiazarian, Radomir S. Stankovic, Jaakko Astola, Heikki Huttunen
    Using a spectral technique, genetic algorithms and decision diagrams for finding unconditional table tests. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:528-531 [Conf]
  134. William N. N. Hung, Xiaoyu Song
    On data address computation for embedded DSP systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:532-535 [Conf]
  135. M. A. Hasan, A. A. Hasan
    Minor and major subspace computation of large matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:536-539 [Conf]
  136. Xiaodong Fan, Guobin Shen, Shipeng Li, T. D. Tran, Ya-Qin Zhang
    Rate-distortion optimization of macroblock-based progressive fine granularity scalable video codec. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:540-543 [Conf]
  137. Lifeng Zhao, Jongwon Kim, C. C. Jay Kuo
    Constant quality rate control for streaming MPEG-4 FGS video. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:544-547 [Conf]
  138. Yuwen He, Feng Wu, Shipeng Li, Yuzhuo Zhong, Shiqiang Yang
    H.26L-based fine granularity scalable video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:548-551 [Conf]
  139. Lauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen
    Effect of CNN shape segmentation on MPEG-4 shape bit-rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:552-555 [Conf]
  140. J. Weber, O. Woywode, H. Guldner, A. L. Baranovski, W. Schwarz
    New method for tailoring ripple and spectral properties of chaotic DC-DC converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:556-559 [Conf]
  141. Hanoch Lev-Ari, Alex M. Stankovic
    Statistical analysis of power spectra of signals governed by Markov chains. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:560-563 [Conf]
  142. Maciej Ogorzalek
    Signal coding and compression based on discrete-time chaos: statistical approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:564-567 [Conf]
  143. Martin Hasler, Thomas Schimming
    Potential of chaos communication over noisy channels - channel coding using chaotic piecewise linear maps. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:568-571 [Conf]
  144. Riccardo Rovatti, Gianluca Mazzini, Gianluca Setti
    An approach to statistical analysis of coarsely time-Markov systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:572-575 [Conf]
  145. J. Shor, Y. Sofer, Y. Polansky, E. Maayan
    Low power voltage regulator for EPROM applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:576-579 [Conf]
  146. S. M. Wang, C. X. Wu
    Full current-mode techniques for high-speed CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:580-582 [Conf]
  147. E. Shen, J. B. Kuo
    0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:583-586 [Conf]
  148. Hong-Yi Huang, Shih-Lun Chen
    Input isolated sense amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:587-590 [Conf]
  149. Hong-Yi Huang, Hsuan-Yi Su
    Low-power 2P2N SRAM with column hidden refresh. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:591-594 [Conf]
  150. Bogdan J. Falkowski, Sudha Kannurao
    Mutual relations and properties of symmetric functions in Walsh spectral domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:595-598 [Conf]
  151. José M. Quintana, Maria J. Avedillo, José L. Huertas
    Simplified Reed-Muller expressions for residue threshold functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:599-602 [Conf]
  152. Lin Jia, R. W. Newcomb
    VLSI realization of four-port ear-type transmission lattice filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:603-606 [Conf]
  153. Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas
    Simple parallel weighted order statistic filter implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:607-610 [Conf]
  154. M. Takahashi, Boon-Keat Tan, H. Iwamura, T. Matsuoka, K. Taniguchi
    A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:611-614 [Conf]
  155. M. Y. Hong
    The reduction of sampling noise in switched-capacitor circuits through spatial oversampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:615-618 [Conf]
  156. I. J. O'Connell, C. Lyden
    A novel double sampled chopper stabilised integrator for switched capacitor Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:619-622 [Conf]
  157. Jacqueline S. Pereira, Antonio Petraglia, M. F. Quelhas
    Approximating linear phase with IIR SC filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:623-626 [Conf]
  158. K. W. H. Ng, V. S. L. Cheung, H. C. Luong
    A 3-V 44-MHz switched-capacitor bandpass filter for digital video application. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:627-630 [Conf]
  159. José L. Ausín, R. Pérez-Aloe, J. Francisco Duque-Carrillo, Guido Torelli, E. Sanchez-Sinencio
    High-selectivity SC filters with continuous digital Q-factor programmability. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:631-634 [Conf]
  160. Anthony Chan Carusone, David A. Johns
    A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:635-638 [Conf]
  161. T. K. Pham, P. E. Allen
    A design of a low-power, high-accuracy, and constant-Q-tuning continuous-time bandpass filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:639-642 [Conf]
  162. Reuben Wilcock, Bashir M. Al-Hashimi
    Application of group delay equalisation in testing fully-balanced OTA-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:643-646 [Conf]
  163. Slawomir Koziel, Stanislaw Szczepanski, Rolf Schaumann
    A general approach to continuous-time Gm-C filters based on matrix descriptions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:647-650 [Conf]
  164. Elvi Räisänen-Ruotsalainen, K. Lasanen, M. Sijander, Juha Kostamovaara
    A low-power 5.4 kHz CMOS gm-C bandpass filter with on-chip center frequency tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:651-654 [Conf]
  165. Keng Hoong Wee, T. Yonezawa, Toshiyuki Nozawa, Tadashi Shibata, Tadahiro Ohmi
    A zone-programmed EEPROM with real-time write monitoring for analog data storage. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:655-658 [Conf]
  166. K. Moolpho, Jitkasem Ngarmnil, K. Nandhasri
    A low-voltage wide-swing FGMOS current amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:659-662 [Conf]
  167. Øivind Næss, Yngvar Berg
    Tunable floating-gate low-voltage transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:663-666 [Conf]
  168. A. N. Mohieldin, A. Emira, E. Sanchez-Sinencio
    A 2-V 11-bit incremental A/D converter using floating gate technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:667-670 [Conf]
  169. Paul D. Smith, Matt Kucic, Richard Ellis, Paul E. Hasler, David V. Anderson
    Mel-frequency cepstrum encoding in analog floating-gate circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:671-674 [Conf]
  170. R. Schreier
    Quadrature mismatch-shaping. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:675-678 [Conf]
  171. A. Fishov, E. Siragusa, J. Welz, E. Fogleman, Ian Galton
    Segmented mismatch-shaping D/A conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:679-682 [Conf]
  172. Zhimin Li, Terri S. Fiez
    Dynamic element matching in low oversampling delta sigma ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:683-686 [Conf]
  173. G. Mulliken, Farhan Adil, Gert Cauwenberghs, Roman Genov
    Delta-sigma algorithmic analog-to-digital conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:687-690 [Conf]
  174. X. Wang, U. Moon, M. Liu, G. C. Temes
    Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:691-694 [Conf]
  175. Keith S. Vallerio, Niraj K. Jha
    Task graph transformation to aid system synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:695-698 [Conf]
  176. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Behavioral synthesis of datapaths with low leakage power. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:699-702 [Conf]
  177. K. Ohashi, M. Kaneko
    Heuristic assignment-driven scheduling for data-path synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:703-706 [Conf]
  178. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering with variable interconnect delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:707-710 [Conf]
  179. Philippe Coussy, Adel Baganne, Eric Martin
    A design methodology for IP integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:711-714 [Conf]
  180. Jun Xin, Ming-Ting Sun, Kangwook Chun, Byung Sun Choi
    Motion re-estimation for HDTV to SDTV transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:715-718 [Conf]
  181. YongQing Liang, Yap-Peng Tan
    Methods and needs for transcoding MPEG-4 fine granularity scalability video. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:719-722 [Conf]
  182. Anthony Vetro, Peng Yin, Bede Liu, Huifang Sun
    Reduced spatio-temporal transcoding using an intra refresh technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:723-726 [Conf]
  183. Mon Wei Wu, C. J. Kuo
    DCT-based edge detector for snapshot images. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:727-730 [Conf]
  184. D. Leon, Sina Balkir, Khalid Sayood
    An evolvable predictor for lossless image compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:731-734 [Conf]
  185. Ka Chun Kwok, Philip K. T. Mok
    Pole-zero tracking frequency compensation for low dropout regulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:735-738 [Conf]
  186. W. E. Bury, J. Dzieza, Dariusz Czarkowski, S. Lewis
    Design and implementation of an Hinfinity controller for a bi-directional DC-DC converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:739-742 [Conf]
  187. A. Rao, W. McIntyre, J. Parry, Un-Ku Moon, Gabor C. Temes
    Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:743-746 [Conf]
  188. M. DiLorenzo del Casale, Nicola Femia, P. Lamberti, V. Mainardi, Giovanni Spagnuolo, Massimo Vitelli
    Nominal and tolerance design of closed-loop controllers for DC-DC voltage regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:747-750 [Conf]
  189. Massimo Vitelli, Giovanni Spagnuolo, Nicola Femia
    Tolerance design of DC-DC switching regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:751-754 [Conf]
  190. S. C. Chan, P. M. Yiu
    A multiplier-less 1-D and 2-D fast Fourier transform-like transformation using sum-of-powers-of-two (SOPOT) coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:755-758 [Conf]
  191. J. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu
    High-performance FIR generation based on a timing-driven architecture and component selection method. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:759-762 [Conf]
  192. Yi Yang, Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy
    An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:763-766 [Conf]
  193. M. A. Hasan
    New algorithms for computing the minimum eigenpair of the generalized symmetric eigenvalue problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:767-770 [Conf]
  194. Bogdan J. Falkowski
    Calculation of Walsh transform on MasPar computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:771-774 [Conf]
  195. Mathieu Renaud, Yvon Savaria
    A linear phase detector for arbitrary clock signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:775-778 [Conf]
  196. Yi-Cheng Chang, E. W. Greeneich
    CMOS auto-ranging PLL for low-voltage wideband systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:779-782 [Conf]
  197. Cyril Lahuec, J. Horan, J. Duigan
    Programmable video clock synthesizer with sub 0.5 ns drift. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:783-786 [Conf]
  198. Yiwu Tang, M. Ismail, S. Bibyk
    A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:787-790 [Conf]
  199. K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez
    A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:791-794 [Conf]
  200. Tommy Kwong-Kin Tsang, Mourad N. El-Gamal
    Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:795-798 [Conf]
  201. V. Chandrasekhar, Kartikeya Mayaram
    Analysis of CMOS RF LNAs with ESD protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:799-802 [Conf]
  202. W. Bakalski, Werner Simbürger, Daniel Kehrer, Hans-Dieter Wohlmuth, M. Rest, Arpad L. Scholtz
    A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz fT Si-bipolar. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:803-806 [Conf]
  203. Sher Jiun Fang, See Taur Lee, David J. Allstot, A. Bellaouar
    A 2 GHz CMOS even harmonic mixer for direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:807-810 [Conf]
  204. Xinping Huang, Mario Caron
    Gain/phase imbalance and DC offset compensation in quadrature modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:811-814 [Conf]
  205. Won Namgoong
    Finite-length synthesis filters for non-uniformly time-interleaved analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:815-818 [Conf]
  206. Lin Luo, Feng Wu, Shipeng Li, Zhenquan Zhuang, Ya-Qin Zhang
    A two-pass optimal motion-threading technique for 3D wavelet video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:819-822 [Conf]
  207. L.-P. Lafrance, M.-A. Cantin, Yvon Savaria, S. H. Sung, Pierre Lavoie
    Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:823-826 [Conf]
  208. Guangming Shi, Xiaoping Li, Licheng Jiao, Zhao Wei
    Adaptive wavelet thresholding for time varying SNR signal denoising. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:827-829 [Conf]
  209. V. Karanko, M. Honkala
    Least squares solution of nearly square overdetermined sparse linear systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:830-833 [Conf]
  210. T. Kimura
    A simple simulation method for analyzing substrate coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:834-837 [Conf]
  211. B. Rajendran, V. Kheterpal, A. Das, J. Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti
    Timing analysis of tree-like RLC circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:838-841 [Conf]
  212. Bogdan J. Falkowski
    Mutual transformations between Haar wavelet and arithmetic spectra. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:842-845 [Conf]
  213. Xun Liu, Marios C. Papaefthymiou
    Incorporation of input glitches into power macromodeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:846-849 [Conf]
  214. M. Hasan, Tughrul Arslan
    A coefficient memory addressing scheme for VLSI implementation of FFT processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:850-853 [Conf]
  215. Nicolas Sklavos, Paris Kitsos, K. Papadomanolakis, Odysseas G. Koufopavlou
    Random number generator architecture and VLSI implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:854-857 [Conf]
  216. Seraphim Poriazis
    The two-phase twisted-ring counter circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:858-861 [Conf]
  217. R. D. Newbould, Jo Dale Carothers, J. J. Rodriguez, W. T. Holman
    A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:862-865 [Conf]
  218. Luca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii
    An adaptive data compression scheme for memory traffic minimization in processor-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:866-869 [Conf]
  219. Tay-Jyi Lin, Chein-Wei Jen
    CASCADE - configurable and scalable DSP environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:870-873 [Conf]
  220. J. H. Takala, T. S. Jarvinen, J. A. Nikara
    Register-based reordering networks for matrix transpose. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:874-877 [Conf]
  221. Paris Kitsos, Nicolas Sklavos, Nicolas G. Koufopavlou
    Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:878-881 [Conf]
  222. D. Zografos, Konstantina Karagianni, Thanos Stouraitis
    VLSI architectures for the implementation of the Wigner distribution. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:882-885 [Conf]
  223. A. Chihoub, Z. B. Miled
    Architectural support for detection of sleepy eye behavior. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:886-889 [Conf]
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