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IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2002 (conf/iscas/2002-5)

  1. J. B. Miller, John C. McEachen, H. H. Loomis Jr., Michael A. Tope, D. B. Copeland
    An analysis of noise in timing-based communications over local area networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:1-4 [Conf]
  2. Xiaojun Wu, Qinye Yin, Hong Zhang
    Lower-complexity direct symbol detector for multiuser MC-CDMA system using antenna array without vector channel estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:5-8 [Conf]
  3. R. Katti, V. V. Bapeswara Rao
    An array based technique for routing messages in distributed double loop networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:9-12 [Conf]
  4. Yu-Nan Lin, David W. Lin
    Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:13-16 [Conf]
  5. A. Laitinen, Marko Hännikäinen, Timo Hämäläinen
    Using SDL a tool for system simulations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:17-20 [Conf]
  6. W. Pietrenko, W. Janke, A. K. Kazimierczuk
    Large-signal time-domain simulation of class-E amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:21-24 [Conf]
  7. Unni Narayanan, Ki-Seok Chung, Taewhan Kim
    Enhanced bus invert encodings for low-power. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:25-28 [Conf]
  8. I. Hattori, A. Kamo, T. Watanabe, H. Asai
    Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:29-32 [Conf]
  9. A. N. Rudiakova, J. V. Rassokhina, Marian K. Kazimierczuk, V. G. Krizhanovski
    High-efficiency microwave BJT power amplifier simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:33-36 [Conf]
  10. Ernesto Chiarantoni, Girolamo Fornarelli, Silvano Vergura
    A new method for efficient time-domain simulation of power electronic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:37-40 [Conf]
  11. Robert M. Fox, Inchang Seo, H. Yeo, O. Jeon
    Leveraged current mirror op amp. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:41-44 [Conf]
  12. Ahmed Emira, Edgar Sánchez-Sinencio, M. Schneider
    Design tradeoffs of CMOS current mirrors using one-equation for all-region model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:45-48 [Conf]
  13. Xuguang Zhang, Ezz I. El-Masry
    A high-performance, low-voltage, body-driven CMOS current mirror. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:49-52 [Conf]
  14. Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
    A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:53-56 [Conf]
  15. W. Tangsrirat, Nobuo Fujii, Wanlop Surakampontorn
    Current-mode leapfrog ladder filters using CDBAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:57-60 [Conf]
  16. Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio
    On-chip spectrum analyzer for built-in testing analog ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:61-64 [Conf]
  17. Jaime Ramírez-Angulo, C. Lackey, Alejandro Díaz-Sánchez
    Compact continuous-time analog rank-order filter implementation in CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:65-68 [Conf]
  18. Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, M. Bruccoleri, G. Betti
    An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:69-72 [Conf]
  19. J. T. Marienborg, Tor Sverre Lande, Mats Erling Høvin
    Neuromorphic noise shaping in coupled neuron populations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:73-76 [Conf]
  20. T. M. Massengill, D. M. Wilson, Paul E. Hasler, David W. Graham
    Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:77-80 [Conf]
  21. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Static timing analysis based circuit-limited-yield estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:81-84 [Conf]
  22. Francky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen
    Regression criteria and their application in different modeling cases. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:85-8 [Conf]
  23. Massimo Conti, Paolo Crippa, Simone Orcioni, M. Pesare, Claudio Turchetti, Loris Vendrame, S. Lucherini
    A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:89-92 [Conf]
  24. Ángel Rodríguez-Vázquez, Gustavo Liñán, Servando Espejo-Meana, Rafael Domínguez-Castro
    Mismatch-induced tradeoffs and scalability of mixed-signal vision chips. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:93-96 [Conf]
  25. Yu Lin, Randall L. Geiger
    Resistors layout for enhancing yield of R-2R DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:97-100 [Conf]
  26. Bill Pontikakis, Mohamed Nekili
    A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:101-104 [Conf]
  27. Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
    Comparative analysis of double-edge versus single-edge triggered clocked storage elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:105-108 [Conf]
  28. Mohammad M. Mansour, Naresh R. Shanbhag
    Simplified current and delay models for deep submicron CMOS digital circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:109-112 [Conf]
  29. Mohab Anis, Mohamed I. Elmasry
    Self-timed MOS current mode logic for digital applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:113-116 [Conf]
  30. Harri Lampinen, Olli Vainio
    Current-sensing completion detection method for standard cell based digital system design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:117-120 [Conf]
  31. Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee
    A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:121-124 [Conf]
  32. Sang-Hee Lee, Myungjin Kim, Keun-Bae Kim
    Modular and efficient architecture for H.263 video codec VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:125-128 [Conf]
  33. Lingfeng Li, Danian Gong, Yun He
    A single-chip real-time programmable video signal processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:129-132 [Conf]
  34. Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen
    High-speed memory-saving architecture for the embedded block coding in JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:133-136 [Conf]
  35. M. Yagi, T. Shibata
    An associative-processor-based mixed signal system for robust grayscale image recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:137-140 [Conf]
  36. Pedro Amaral, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção
    An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:141-144 [Conf]
  37. A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
    SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:145-148 [Conf]
  38. G. A. Al-Rawi
    A new offset measurement and cancellation technique for dynamic latches. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:149-152 [Conf]
  39. Roman Genov, Gert Cauwenberghs
    Charge-based MOS correlated double sampling comparator and folding circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:153-156 [Conf]
  40. Lauri Sumanen, Mikko Waltari, Väinö Hakkarainen, Kari Halonen
    CMOS dynamic comparators for pipeline A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:157-160 [Conf]
  41. Aleksandar Tasic, Wouter A. Serdijn
    Concept of phase-noise tuning of bipolar voltage-controlled oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:161-164 [Conf]
  42. P. Kallam, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
    An improved Q-tuning scheme and a fully symmetric OTA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:165-168 [Conf]
  43. Bo Shi, Weiyun Shan, Pietro Andreani
    A 57-dB image band rejection CMOS G/sub m/-C polyphase filter with automatic frequency tuning for Bluetooth. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:169-172 [Conf]
  44. Mingdeng Chen, J. Silva-Martinez, S. Rokhsaz, M. Robinson
    A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05/spl deg/ equiripple linear phase filter with automatic tuning system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:173-176 [Conf]
  45. Aydin I. Karsilayan, Sung-Ling Huang, Jader A. De Lima
    Automatic tuning of linearly tunable high-Q filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:177-180 [Conf]
  46. F. Silveira, D. Flandre
    A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:181-184 [Conf]
  47. V. S. L. Cheung, H. Luong, Mansun Chan
    A 0.9-V 0.2-/spl mu/W CMOS single-opamp-based switched-opamp /spl Sigma//spl Delta/ modulator for pacemaker applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:185-188 [Conf]
  48. Christopher D. Salthouse, Rahul Sarpeshkar
    A micropower band-pass filter for use in bionic ears. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:189-192 [Conf]
  49. R. Rieger, J. Taylor, N. Donaldson
    Low noise preamplifier design for nerve cuff electrode recording systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:193-196 [Conf]
  50. Reid R. Harrison
    A low-power, low-noise CMOS amplifier for neural recording applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:197-200 [Conf]
  51. R. Murali, Lihui Wang, Blanca Austin, James D. Meindl
    Low-power circuit advantages of the scaled accumulation FET. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:201-204 [Conf]
  52. L.-E. Wernersson, E. Lind, P. Lindstrom, Pietro Andreani
    Circuits and devices with integrated VFETs and RTDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:205-208 [Conf]
  53. Shin-ichi O'uchi, Minoru Fujishima, Koichiro Hoh
    An 8-qubit quantum-circuit processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:209-212 [Conf]
  54. Luigi Fortuna, Mattia Frasca, Alessandro Rizzo
    Self-organising behavior of arrays of nonidentical Josephson junctions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:213-216 [Conf]
  55. Koray Karahaliloglu, Sina Balkir
    Image processing with quantum dot nanostructures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:217-220 [Conf]
  56. M. Lee, R. B. Anna, Jui-Chu Lee, Scott M. Parker, Kim M. Newton
    A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contact. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:221-224 [Conf]
  57. J. Roychowdhury
    Theory and algorithms for RF sensitivity computation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:225-228 [Conf]
  58. Jian-Yi Wu, Steven B. Bibyk
    Robust design with virtual tests of mixed-signal circuits in VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:229-232 [Conf]
  59. Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim
    An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:233-236 [Conf]
  60. D. Ozis, Kartikeya Mayaram, Terri S. Fiez
    An efficient modeling approach for substrate noise coupling analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:237-240 [Conf]
  61. A. C.-W. Yu, Oscar C. Au, Bing Zeng
    Removing of blocking artefacts using error-compensation interpolation and fast adaptive spatial-varying filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:241-244 [Conf]
  62. Jiho Park, Dong-Chul Park, Robert J. Marks II, Mohamed A. El-Sharkawi
    Block loss recovery in DCT image encoding using POCS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:245-248 [Conf]
  63. John E. Kleider, Glen P. Abousleman
    Image quality optimization using computationally efficient variable QoS multicarrier bit-allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:249-252 [Conf]
  64. P. Carrai, Ingrid Heynderickx, Paolo Gastaldo, Rodolfo Zunino
    Image quality assessment by using neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:253-256 [Conf]
  65. Ken-Chung Ho
    Non-causal error diffusion for image halftoning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:257-260 [Conf]
  66. K. Nandhasri, Jitkasem Ngarmnil, K. Moolpho
    A 2.8V RWDM BTL Class-D power amplifier using an FGMOS comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:261-264 [Conf]
  67. Cheung Fai Lee, Philip K. T. Mok
    On-chip current sensing technique for CMOS monolithic switch-mode power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:265-268 [Conf]
  68. Gerard Villar, Eduard Alarcón, Herminio Martínez, Domingo Biel, Eva Vidal, Alberto Poveda
    Averaging circuit for switching power converter control: a CMOS current-mode integrated implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:269-272 [Conf]
  69. Stephen P. Carullo, Chika O. Nwankpa
    Analysis of measurement delay errors in an Ethernet based communication infrastructure for power systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:273-276 [Conf]
  70. Chris J. Dafis, Chika O. Nwankpa
    A nonlinear observability formulation for power systems incorporating generator dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:277-280 [Conf]
  71. Somchart Chokchaitam, Masahiro Iwahashi
    Lossless/lossy coding gain to evaluate coding performance of the lossless/lossy wavelet. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:281-284 [Conf]
  72. X. M. Xie, S. C. Chan, T. I. Yuk
    On the theory and design of a class of perfect-reconstruction nonuniform cosine-modulated filter-banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:285-288 [Conf]
  73. H. Johansson
    Multirate approximately linear-phase IIR filter structures for arbitrary bandwidths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:289-292 [Conf]
  74. Behrouz Nowrouzian, Arthur T. G. Fuller, M. N. S. Swamy
    An alternative approach to the design and synthesis of higher-order Bode-type variable-amplitude wave-digital equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:293-296 [Conf]
  75. Shin'ichi Shiraishi, Miki Haseyama, Hideo Kitajima
    A cost-effective and high-precision architecture for CORDIC-based adaptive lattice filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:297-300 [Conf]
  76. Robert J. Butera, N. McSpadden, J. Mason
    Theory and design of a bio-inspired multistable oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:301-304 [Conf]
  77. Herbert H. C. Iu, C. K. Tse, V. Pjevalica, Y. M. Lai
    Analysis of Hopf bifurcation in parallel-connected boost converters via averaged models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:305-308 [Conf]
  78. Y. Aruga, T. Endo, A. Hasegawa
    Bifurcation of modes in three-coupled oscillators with the increase of nonlinearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:309-312 [Conf]
  79. S. Moro, T. Matsumoto
    Phase pattern switching in star-coupled Wien-bridge oscillators driven by pulse train. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:313-316 [Conf]
  80. Masayuki Yamauchi, Yoshifumi Nishio, Akio Ushida
    Analysis of phase-waves in coupled oscillators as a ladder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:317-320 [Conf]
  81. Bogdan J. Falkowski, Susanto Rahardja
    Boolean verification with fastest LIA transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:321-324 [Conf]
  82. Jiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang
    A don't-care based image circuit for function verification. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:325-328 [Conf]
  83. Yutao Hu, Kartikeya Mayaram
    An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:329-332 [Conf]
  84. A. Salem
    Semi-formal verification of VHDL-AMS descriptions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:333-336 [Conf]
  85. Yi Feng, Eduard Cerny
    Variable ordering on multiway decision graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:337-340 [Conf]
  86. Aloys Mvuma, Shotaro Nishimura, Takao Hinamoto
    Adaptive optimization of notch bandwidth of an IIR filter used to suppress narrow-band interference. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:341-344 [Conf]
  87. Mariane R. Petraglia, R. T. B. Vasconcellos
    Steady-state analysis of a subband adaptive algorithm with critical sampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:345-348 [Conf]
  88. Wei Xing Zheng
    An alternative method for noisy autoregressive signal estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:349-352 [Conf]
  89. Yusuke Tsuda, Tetsuya Shimamura
    An improved NLMS algorithm for channel equalization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:353-356 [Conf]
  90. S. H. Leung, Y. Xiong, J. F. Weng, C. F. So, W. H. Lau
    Performance analysis of nonlinear RLS in mixture noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:357-360 [Conf]
  91. J. M. P. Langlois, Dhamin Al-Khalili
    Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:361-364 [Conf]
  92. Wang-Chi Cheng, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A 1.2 V 900 MHz CMOS mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:365-368 [Conf]
  93. Francisco Cardells-Tormo, A. Valls-Coquillat
    Optimized FPGA-implementation of quadrature DDS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:369-372 [Conf]
  94. Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
    A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:373-376 [Conf]
  95. M. A. R. Eltokhy, B.-K. Tan, T. Matsuoka, K. Taniguchi
    A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:377-380 [Conf]
  96. K. Aoyama
    A reconfigurable logic circuit based on threshold elements with a controlled floating gate. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:381-384 [Conf]
  97. Yngvar Berg, Øivind Næss, Snorre Aunet, R. Jensen, Mats Høvin
    Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:385-388 [Conf]
  98. Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda
    High-speed low-power logic gates using floating gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:389-392 [Conf]
  99. Trond Ytterdal, Snorre Aunet
    Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:393-396 [Conf]
  100. Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande
    A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:397-400 [Conf]
  101. A. Costantini, P. A. Traverso, G. Vannini
    Power amplifier ACPR simulation using standard harmonic balance tools. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:401-404 [Conf]
  102. J. Shorb, David J. Allstot, R. Roze
    Class AB-D-G line driver for central office asymmetric digital subscriber line systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:405-408 [Conf]
  103. M. B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi
    A low-power subscriber line interface circuit in a high-voltage CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:409-412 [Conf]
  104. T. Bourdi, A. Borjak, Izzet Kale
    Agile multi-band delta-sigma frequency synthesizer architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:413-416 [Conf]
  105. M. Schobinger, S. R. Meier
    A low-cost point-to-multi-point access system based on OFDM transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:417-420 [Conf]
  106. U. Singh, M. Green
    Dynamics of high-frequency CMOS dividers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:421-424 [Conf]
  107. J. Van den Keybus, B. Bolsens, J. Driesen, R. Belmans
    Power line communication front-ends based on ADSL technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:425-428 [Conf]
  108. Esa Tiiliharju, Kari Halonen
    A quadrature-modulator for 0.6-2.6 GHz with frequency doubler. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:429-432 [Conf]
  109. Alyssa B. Apsel, Andreas G. Andreou, J. Liu
    A 6 channel array of 5 milliwatt, 500 MHz optical receivers in .5 /spl mu/m SOS CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:433-436 [Conf]
  110. Mostafa M. El Said, M. L. Elmasry
    An improved ROM compression technique for direct digital frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:437-440 [Conf]
  111. Patrick Mitran, Felix Beaudoin, Mourad N. El-Gamal
    A 2.5 Gbit/s CMOS optical receiver frontend. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:441-444 [Conf]
  112. Jongrit Lerdworatawee, Won Namgoong
    MMSE matching for low noise amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:445-448 [Conf]
  113. Aleksandar Tasic, Wouter A. Serdijn
    Concept of spectrum-signal transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:449-452 [Conf]
  114. Cheng-Shing Wu, An-Yeu Wu
    A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:453-456 [Conf]
  115. S. Soliman, F. Yuan, Kaamran Raahemifar
    An overview of design techniques for CMOS phase detectors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:457-460 [Conf]
  116. V. Balan, T. Pan
    A crystal oscillator with automatic amplitude control and digitally controlled pulling range of +-100 ppm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:461-464 [Conf]
  117. M. Kaneko, J. Yokoyama, S. Tayu
    3D scheduling based on code space exploration for dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:465-468 [Conf]
  118. Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
    Performance optimization of multiple memory architectures for DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:469-472 [Conf]
  119. Cesare Alippi, Andrea Galbusera, Marco Stellini
    An application level synthesis methodology for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:473-476 [Conf]
  120. Jochen Mades, D. E. Schwarz, Manfred Glesner
    A discrete algorithm for the regularization of hierarchical VHDL-AMS models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:477-480 [Conf]
  121. Yoonseo Choi, Taewhan Kim
    Address code optimization using code scheduling for digital signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:481-484 [Conf]
  122. D. W. Graham, P. Hasler
    Capacitively-coupled current conveyer second-order section for continuous-time bandpass filtering and cochlea modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:485-488 [Conf]
  123. Paul D. Smith, Matt Kucic, Paul E. Hasler
    Accurate programming of analog floating-gate arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:489-492 [Conf]
  124. C. Duffy, Ethan Farquhar, Paul E. Hasler
    Practical issues using e-pot circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:493-496 [Conf]
  125. H. Sato, A. Hyogo, K. Sekine
    A V/sub t/-zero equivalent MOSFET and its applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:497-500 [Conf]
  126. Johannes Goplen Lomsdalen, Yngvar Berg, Renè Jensen
    A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency tripler. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:501-504 [Conf]
  127. Tadashi Suetsugu, Marian K. Kazimierczuk
    Voltage-clamped class E amplifier with a Zener diode across the choke coil. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:505-508 [Conf]
  128. D. V. Chernov, Marian K. Kazimierczuk, V. G. Krizhanovski
    Class-E MOSFET low-voltage power oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:509-512 [Conf]
  129. Alberto Reatti, L. Pellegrini, Marian K. Kazimierczuk
    Impact of boost converter parameters on open-loop dynamic performance for DCM. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:513-516 [Conf]
  130. A. N. Rudiakova, Marian K. Kazimierczuk, J. V. Rassokhin, V. G. Krizhanovski
    Class-N high-frequency power amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:517-520 [Conf]
  131. A. Alsharqawi, Issa Batarseh
    Generalized state-plane analysis of soft-switching DC-DC converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:521-524 [Conf]
  132. K. Rustom, Wenkai Wu, Weihong Qiu, Issa Batarseh
    Asymmetry half bridge soft-switching PFC converter with direct energy transfer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:525-528 [Conf]
  133. Ming-Dou Ker, Kuo-Chun Hsu
    On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:529-532 [Conf]
  134. Ming-Dou Ker, Che-Hao Chuang
    ESD protection circuits with novel MOS-bounded diode structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:533-536 [Conf]
  135. Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang
    Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:537-540 [Conf]
  136. Li Ding 0002, Pinaki Mazumder
    Modified long channel model for analytical study of DSM circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:541-544 [Conf]
  137. Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, T. Sakurai
    CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:545-548 [Conf]
  138. Jiun-In Guo, Chien-Chang Lin
    A new hardware efficient design for the one dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:549-552 [Conf]
  139. E. Marconetti, R. Guenard, D. Savage, P. Crowe, I. Epelde, L. Bradley, Fabrizio Calì
    A fully programmable Reed Solomon 8-bit codec based on a re-shaped Berlekamp Massey algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:553-556 [Conf]
  140. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
    Memory arrangements in turbo decoders using sliding-window BCJR algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:557-560 [Conf]
  141. Jung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim
    Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:561-564 [Conf]
  142. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:565-568 [Conf]
  143. Devrim Yilmaz Aksin, Franco Maloberti
    Very high-speed BJT buffer for track-and-hold amplifiers with enhanced linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:569-572 [Conf]
  144. F. Vessal, C. Andre T. Salama
    A bipolar 2-GSample/s track-and-hold amplifier (THA) in 0.35 /spl mu/m SiGe technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:573-576 [Conf]
  145. Darius Jakonis, Christer Svensson
    A 1 GHz linearized CMOS track-and-hold circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:577-580 [Conf]
  146. Preetam Tadeparthy, M. Das
    Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:581-584 [Conf]
  147. Sameer R. Sonkusale, Jan Van der Spiegel
    A low distortion MOS sampling circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:585-588 [Conf]
  148. Huanzhang Huang, E. K. Lee
    Frequency and Q tuning techniques for continuous-time bandpass sigma-delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:589-592 [Conf]
  149. Bo Xia, Shouli Yan, E. Sanchez-Sinencio
    An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:593-596 [Conf]
  150. A. D. Fifield, D. K. Allee
    Dynamic tuning of the noise transfer function of high order delta-sigma analog to digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:597-600 [Conf]
  151. Aydin I. Karsilayan, Taner Sumesaglam
    Digital tuning of continuous-time high-Q filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:601-604 [Conf]
  152. J. R. Moritz, Y. Sun
    Automatic tuning of high frequency, high Q, multiple loop feedback bandpass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:605-608 [Conf]
  153. Christal Gordon, Paul E. Hasler
    Biological learning modeled in an adaptive floating-gate system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:609-612 [Conf]
  154. Ricardo Carmona, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez
    Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:613-616 [Conf]
  155. Mats Høvin, Dag T. Wisland, Yngvar Berg, J. T. Marienborg, Tor Sverre Lande
    Delta-sigma modulation in single neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:617-620 [Conf]
  156. Sandro A. P. Haddad, Wouter A. Serdijn
    Mapping the wavelet transform onto silicon: the dynamic translinear approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:621-624 [Conf]
  157. T. Yamasaki, T. Taguchi, T. Shibata
    Low-power CDMA analog matched filters based on floating-gate technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:625-628 [Conf]
  158. Lei Gao, Lina J. Karam, Martin Reisslein, Glen P. Abousleman
    Error-resilient image coding and transmission over wireless channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:629-632 [Conf]
  159. M. Mowafi, Nan Jiang, Thomas P. Caudell, Wei Shu, Min-You Wu
    Real-time transmission of stereo images over the access grid. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:633-636 [Conf]
  160. Ch. V. Verikoukis
    An adaptive control of the request access bandwidth of the DQRUMA for providing the QoS in an OFDM-based W-ATM system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:637-640 [Conf]
  161. Hua Cai, Guobin Shen, Zixiang Xiong, Shipeng Li, Bing Zeng
    An optimal packetization scheme for fine granularity scalable bitstream. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:641-644 [Conf]
  162. Li Ding 0002, Pinaki Mazumder, David Blaauw
    Crosstalk noise estimation using effective coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:645-648 [Conf]
  163. H. Kubota, A. Kamo, T. Watanabe, H. Asai
    Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:649-552 [Conf]
  164. Yehea I. Ismail
    Evaluating noise pulses in RC networks due to capacitive coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:653-656 [Conf]
  165. Chao Xu, F. Barber, K. R. Laker, Jan Van der Spiegel
    Analysis of clock buffer phase noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:657-660 [Conf]
  166. Paolo Gastaldo, Rodolfo Zunino
    Hausdorff distance for target detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:661-664 [Conf]
  167. Ibrahim Cem Baykal, Roberto Muscedere, Graham A. Jullien
    On the use of hash functions for defect detection in textures for in-camera web inspection systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:665-668 [Conf]
  168. Liang Tao, H. K. Kwan
    Automatic localization of human eyes in complex background. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:669-672 [Conf]
  169. Madhusudhana Gargesha, Sethuraman Panchanathan
    Face detection from color images by iterative thresholding on skin probability maps. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:673-676 [Conf]
  170. Yih-Haw Jan, David W. Lin
    Extraction of video objects by combined motion and edge analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:677-680 [Conf]
  171. J. Driesen, R. Belmans
    Time-frequency analysis in power measurement using complex wavelets. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:681-684 [Conf]
  172. Lisandro Lovisolo, Eduardo A. B. da Silva, Marco A. M. Rodrigues, Paulo S. R. Diniz
    Coherent decompositions of power systems signals using damped sinusoids with applications to denoising. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:685-688 [Conf]
  173. Hanoch Lev-Ari, Alex M. Stankovic
    Defining reactive power in circuit transients via local Fourier coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:689-692 [Conf]
  174. Vaibhav Donde, Ian A. Hiskens
    Analysis of limit cycle stability in a tap-changing transformer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:693-696 [Conf]
  175. Jie Wan, Karen Nan Miu
    Zonal load estimation studies in radial power distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:697-700 [Conf]
  176. Soo-Chang Pei, Peng-Hua Wang
    Maximally flat allpass fractional Hilbert transformers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:701-704 [Conf]
  177. Hiroshi Hasegawa, M. Nakagawa, Isao Yamada, Kohichi Sakaniwa
    A truncated polynomial interpolation theorem and its application to the WLS design of IIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:705-708 [Conf]
  178. T. Hinamoto, H. Ohnishi
    Minimization of roundoff noise in state-space digital filters using error feedback and coordinate transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:709-712 [Conf]
  179. Chien-Cheng Tseng
    Design of variable fractional delay allpass filter using weighted least squares method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:713-716 [Conf]
  180. Andrzej Tarczynski
    Problem dimensionality reduction in design of optimal IIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:717-720 [Conf]
  181. L. Schwoerer
    VLSI suitable synchronization algorithms and architecture for IEEE 802.11a Physical Layer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:721-724 [Conf]
  182. A. Kansal, Uday B. Desai
    Mobility support for Bluetooth public access. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:725-728 [Conf]
  183. Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park
    Area-efficient digital baseband module for Bluetooth wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:729-732 [Conf]
  184. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:733-736 [Conf]
  185. D. A. F. Ei-Dib, Mohamed I. Elmasry
    Low-power register-exchange Viterbi decoder for high-speed wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:737-740 [Conf]
  186. Shuqing Zhao, Daniel Gajski
    Modeling a new RTL semantics in C++. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:741-744 [Conf]
  187. Sudha Kannurao, Bogdan J. Falkowski
    Identification of complement single variable symmetry in Boolean functions through Walsh transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:745-748 [Conf]
  188. T. Ozawa
    Efficient algorithms for planar embedding of graphs with constraints in placing specified vertices on face boundaries. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:749-752 [Conf]
  189. Bogdan J. Falkowski
    Algorithms for fast arithmetic transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:753-756 [Conf]
  190. Bogdan J. Falkowski
    Generalized multi-polarity Haar transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:757-760 [Conf]
  191. K. S. Yeung, S. C. Chan
    Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:761-764 [Conf]
  192. Abdellah Kacha, Khier Benmahammed
    Tracking instantaneous frequency using two-sided linear prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:765-768 [Conf]
  193. A. Yonemoto, Takashi Hisakado, Kohshi Okumura
    An improvement of convergence of FFT-based numerical inversion of Laplace transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:769-772 [Conf]
  194. Andrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale
    Designing multiplier blocks with low logic depth. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:773-776 [Conf]
  195. Masayuki Kawamata, Shunsuke Koshita
    On the invariance of second-order modes under frequency transformation in 2-D separable denominator digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:777-780 [Conf]
  196. Arash Reyhani-Masoleh, M. Anwar Hasan
    Efficient digit-serial normal basis multipliers over GF(2/sup m/). [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:781-784 [Conf]
  197. Zhan Yu
    Low power finite field multiplication and division in re-configurable Reed-Solomon codec. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:785-788 [Conf]
  198. Zhiyuan Yan, Dilip V. Sarwate
    Systolic architectures for finite field inversion and division. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:789-792 [Conf]
  199. Jae H. Baek, J. Y. Kang, Myung Hoon Sunwoo
    Design of a high-speed Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:793-796 [Conf]
  200. Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
    Tradeoff analysis of FPGA based elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:797-800 [Conf]
  201. Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Power characterization of digital filters implemented on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:801-804 [Conf]
  202. J. C. B. Mattos, L. Carro
    Efficient architecture for FPGA-based microcontrollers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:805-808 [Conf]
  203. Chuanjun Zhang, Frank Vahid
    A power-configurable bus for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:809-812 [Conf]
  204. Wei Wang, M. N. S. Swamy, M. Omair Ahmad
    A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:813-816 [Conf]
  205. Kahou Wong
    Stability study of a voltage-mode buck regulator using system poles approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:817-820 [Conf]
  206. Edith Kussener, Hervé Barthélemy, A. Malherbe, A. Kaiser
    Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:821-824 [Conf]
  207. C. K. Chava, J. Silva-Martinez
    A robust frequency compensation scheme for LDO regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:825-828 [Conf]
  208. Itsda Boonyaroonate, S. Mori
    A compact DC/AC inverter for automotive application. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:829-832 [Conf]
  209. Siew Kuok Hoon, Jun Chen, Franco Maloberti
    An improved bandgap reference with high power supply rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:833-836 [Conf]
  210. R. Echavarría, V. Sanchez, Mario Ponce, M. Cotorogea, A. Claudio
    Analysis of a power topology for a quasi-resonant fast on-load tap changing regulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:837-840 [Conf]
  211. Brad Bryant, Marian K. Kazimierczuk
    Derivation of the buck-boost PWM DC-DC converter circuit topology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:841-844 [Conf]
  212. R. Razali, V. Subbiah, M. A. Choudhury, R. Yusof
    Performance analysis of online dual slope delta modulated PWM inverter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:845-848 [Conf]
  213. Alberto Reatti, L. Pellegrini, Marian K. Kazimierczuk
    Measurement of open-loop small-signal control-to-output transfer function of a PWM boost converter operated in DCM. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:849-851 [Conf]
  214. J. Morud
    A 1 MHz voltage multiplier design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:856-859 [Conf]
  215. Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
    A SET quantizer circuit aiming at digital communication system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:860-863 [Conf]
  216. Tetsuya Uemura, Pinaki Mazumder
    Rise time analysis of MOBILE circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:864-867 [Conf]
  217. R. van de Haar, J. Hoekstra, R. H. Klunder
    A SPICE model for single electronics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:868-871 [Conf]
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NOTICE2
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