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Conferences in DBLP

International Symposium on Low Power Electronics and Design (islped)
2005 (conf/islped/2005)

  1. Dennis Buss
    Technology and design challenges for mobile communication and computing products. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:1- [Conf]
  2. Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic
    FinFET-based SRAM design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:2-7 [Conf]
  3. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
    Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:8-13 [Conf]
  4. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:14-19 [Conf]
  5. Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester
    Analysis and mitigation of variability in subthreshold design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:20-25 [Conf]
  6. Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
    Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:26-29 [Conf]
  7. Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
    Instruction packing: reducing power and delay of the dynamic scheduling logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:30-35 [Conf]
  8. Ahmad Zmily, Christos Kozyrakis
    Energy-efficient and high-performance instruction fetch using a block-aware ISA. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:36-41 [Conf]
  9. Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
    Energy-aware fetch mechanism: trace cache and BTB customization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:42-47 [Conf]
  10. Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
    Understanding the energy efficiency of SMT and CMP with multiclustering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:48-53 [Conf]
  11. Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas
    A simple mechanism to adapt leakage-control policies to temperature. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:54-59 [Conf]
  12. Emmanuel Allier, J. Goulier, Gilles Sicard, A. Dezzani, E. André, Marc Renaudin
    A 120nm low power asynchronous ADC. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:60-65 [Conf]
  13. Xinhua Chen, Qiuting Huang
    A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:66-71 [Conf]
  14. Douglas Mercer
    A low power current steering digital to analog converter in 0.18 Micron CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:72-77 [Conf]
  15. Peter C. S. Scholtens, David Smola, Maarten Vertregt
    Systematic power reduction and performance analysis of mismatch limited ADC designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:78-83 [Conf]
  16. Lucas Andrew Milner, Gabriel A. Rincón-Mora
    A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:84-89 [Conf]
  17. Lei He, Mike Hutton, Tim Tuan, Steve Wilton
    Challenges and opportunities for low power FPGAs in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:90- [Conf]
  18. Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
    A GHz-class charge recovery logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:91-94 [Conf]
  19. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Low-power fanout optimization using multiple threshold voltage inverters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:95-98 [Conf]
  20. Srinivasa R. Sridhara, Naresh R. Shanbhag
    A low-power bus design using joint repeater insertion and coding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:99-102 [Conf]
  21. Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar
    An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:103-106 [Conf]
  22. Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
    A low-power, multichannel gated oscillator-based CDR for short-haul applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:107-110 [Conf]
  23. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:111-114 [Conf]
  24. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
    Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:115-118 [Conf]
  25. Xueqi Cheng, Michael S. Hsiao
    Region-level approximate computation reuse for power reduction in multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:119-122 [Conf]
  26. Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
    Joint exploration of architectural and physical design spaces with thermal consideration. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:123-126 [Conf]
  27. Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark
    Coordinated, distributed, formal energy management of chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:127-130 [Conf]
  28. Vineet Wason, Kaustav Banerjee
    A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:131-136 [Conf]
  29. Yu Ching Chang, King Ho Tam, Lei He
    Power-optimal repeater insertion considering Vdd and Vth as design freedoms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:137-142 [Conf]
  30. Azadeh Davoodi, Ankur Srivastava
    Probabilistic dual-Vth leakage optimization under variability. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:143-148 [Conf]
  31. David G. Chinnery, Kurt Keutzer
    Linear programming for sizing, Vth and Vdd assignment. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:149-154 [Conf]
  32. Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo
    An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:155-160 [Conf]
  33. Marco Lanuzza, Martin Margala, Pasquale Corsonello
    Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:161-166 [Conf]
  34. Il-soo Lee, Tony Ambler
    Two efficient methods to reduce power and testing time. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:167-172 [Conf]
  35. Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron
    Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:173-178 [Conf]
  36. Seokkee Kim, Soo-Ik Chae
    Complexity reduction in an nRERL microprocessor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:180-185 [Conf]
  37. Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
    Driver pre-emphasis techniques for on-chip global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:186-191 [Conf]
  38. Jie Gu, Chris H. Kim
    Multi-story power delivery for supply noise reduction and low voltage operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:192-197 [Conf]
  39. Rabiul Islam, Adam Brand, Dave Lippincott
    Low power SRAM techniques for handheld products. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:198-202 [Conf]
  40. Masaya Sumita
    High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:203-208 [Conf]
  41. Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen
    An evaluation of code and data optimizations in the context of disk power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:209-214 [Conf]
  42. Guiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Thomas F. La Porta
    Optimizing sensor movement planning for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:215-220 [Conf]
  43. Gilberto Contreras, Margaret Martonosi
    Power prediction for intel XScale processors using performance monitoring unit events. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:221-226 [Conf]
  44. William R. Dieter, Srabosti Datta, Wong Key Kai
    Power reduction by varying sampling rate. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:227-232 [Conf]
  45. Ali Iranli, Morteza Maleki, Massoud Pedram
    Energy efficient strategies for deployment of a two-level wireless sensor network. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:233-238 [Conf]
  46. Maha Nizam, Farid N. Najm, Anirudh Devgan
    Power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:239-244 [Conf]
  47. Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan
    The need for a full-chip and package thermal model for thermally optimized IC designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:245-250 [Conf]
  48. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Peak temperature control and leakage reduction during binding in high level synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:251-256 [Conf]
  49. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:257-262 [Conf]
  50. Andrew B. Kahng, Swamy Muddu, Puneet Sharma
    Defocus-aware leakage estimation and control. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:263-268 [Conf]
  51. Peng Rong, Massoud Pedram
    Hierarchical power management with application to scheduling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:269-274 [Conf]
  52. W. L. Bircher, M. Valluri, J. Law, L. K. John
    Runtime identification of microprocessor energy saving opportunities. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:275-280 [Conf]
  53. Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger
    Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:281-286 [Conf]
  54. Fen Xie, Margaret Martonosi, Sharad Malik
    Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:287-292 [Conf]
  55. Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
    Power-aware code scheduling for clusters of active disks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:293-298 [Conf]
  56. Chandra Narayanaswami
    Wearable computing: a catalyst for business and entertainment. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:302- [Conf]
  57. Dongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu
    Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:303-306 [Conf]
  58. Farhan Simjee, Pai H. Chou
    Accurate battery lifetime estimation using high-frequency power profile emulation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:307-310 [Conf]
  59. Maurice Meijer, José Pineda de Gyvez, Ralph Otten
    On-chip digital power supply control for system-on-chip applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:311-314 [Conf]
  60. Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah
    Self-timed circuits for energy harvesting AC power supplies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:315-318 [Conf]
  61. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
    A tunable bus encoder for off-chip data buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:319-322 [Conf]
  62. Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
    Fast configurable-cache tuning with a unified second-level cache. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:323-326 [Conf]
  63. Guangyu Chen, Mahmut T. Kandemir
    Dataflow analysis for energy-efficient scratch-pad memory management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:327-330 [Conf]
  64. Tali Moreshet, R. Iris Bahar, Maurice Herlihy
    Energy reduction in multiprocessor systems using transactional memory. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:331-334 [Conf]
  65. Jerry Hom, Ulrich Kremer
    Inter-program optimizations for conserving disk energy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:335-338 [Conf]
  66. Yao Guo, Mahmoud Ben Naser, Csaba Andras Moritz
    PARE: a power-aware hardware data prefetching engine. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:339-344 [Conf]
  67. Jia-Jhe Li, Yuan-Shin Hwang
    Snug set-associative caches: reducing leakage power while improving performance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:345-350 [Conf]
  68. Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao
    An energy efficient TLB design methodology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:351-356 [Conf]
  69. Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic
    Synonymous address compaction for energy reduction in data TLB. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:357-362 [Conf]
  70. Tohru Ishihara, Farzan Fallah
    A non-uniform cache architecture for low power system design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:363-368 [Conf]
  71. Seongmoo Heo, Krste Asanovic
    Replacing global wires with an on-chip network: a power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:369-374 [Conf]
  72. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    A low-power crossroad switch architecture and its core placement for network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:375-380 [Conf]
  73. Koushik Niyogi, Diana Marculescu
    System level power and performance modeling of GALS point-to-point communication interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:381-386 [Conf]
  74. Krishnan Srinivasan, Karam S. Chatha
    A technique for low energy mapping and routing in network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:387-392 [Conf]
  75. Hai Huang, Kang G. Shin, Charles Lefurgy, Tom W. Keller
    Improving energy efficiency by making DRAM less randomly accessed. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:393-398 [Conf]
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NOTICE2
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