Conferences in DBLP
Edwin de Angel , Earl E. Swartzlander Jr. Survey of low power techniques for ROMs. [Citation Graph (0, 0)][DBLP ] Conf ] June Jiang , Kan Lu , Uming Ko High-performance, low-power design techniques for dynamic to static logic interface. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Somasekhar , Kaushik Roy LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Stefano Quer System-level power optimization of special purpose applications: the beach solution. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Philippe Diguet , Sven Wuytack , Francky Catthoor , Hugo De Man Formalized methodology for data reuse exploration in hierarchical memory mappings. [Citation Graph (0, 0)][DBLP ] Conf ] Mutsunori Igarashi , Kimiyoshi Usami , Kazutaka Nogami , Fumihiro Minami , Yukio Kawasaki , Takahiro Aoki , Midori Takano , Chiharo Mizuno , Takashi Ishikawa , Masahiro Kanazawa , Shinji Sonoda , Makoto Ichida , Naoyuki Hatanaka A low-power design method using multiple supply voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Mattisson Minimizing power dissipation of cellular phones. [Citation Graph (0, 0)][DBLP ] Conf ] Donald A. Hitko , Theodore L. Tewksbury , Charles Sodini A 1V, 5mW, 1.8GHz balanced voltage-controlled oscillator with an integrated resonator. [Citation Graph (0, 0)][DBLP ] Conf ] Mats Erling Høvin , S. Kiaei , Tor Sverre Lande Delta Sigma frequency-to-time conversion by triangularly weighted ZC counter. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishna Kumthekar , In-Ho Moon , Fabio Somenzi A symbolic algorithm for low-power sequential synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwan Shin , Kiyoung Choi Low power high level synthesis by increasing data correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Emad N. Farag , Ran-Hong Yan , Mohamed I. Elmasry A programmable power-efficient decimation filter for software radios. [Citation Graph (0, 0)][DBLP ] Conf ] Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Yu Chen , Debashree Ghosh Techniques for low energy software. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Nicol , Patrik Larsson Low power multiplication for FIR filters. [Citation Graph (0, 0)][DBLP ] Conf ] Morgan Hirosuke Miki , Gen Fujita , Takao Onoye , Isao Shirakawa Low-power H.263 video CoDec dedicated to mobile computing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason J. Brown , Danny Z. Chen , Garrison W. Greenwood , Xiaobo Hu , Richard W. Taylor Scheduling for power reduction in a real-time system. [Citation Graph (0, 0)][DBLP ] Conf ] Premal Buch , Christopher K. Lennard , A. Richard Newton Engineering change for power optimization using global sensitivity and synthesis flexibility. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , Michael Theobald Synthesis of low-power asynchronous circuits in a specified environment. [Citation Graph (0, 0)][DBLP ] Conf ] Yibin Ye , Kaushik Roy , Georgios I. Stamoulis Quasi-static energy recovery logic and supply-clock generation circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bum-Sik Kim , Dae-Hyum Chung , Lee-Sup Kim A new 4-2 adder and booth selector for low power MAC unit. [Citation Graph (0, 0)][DBLP ] Conf ] A. Schlaffer , Josef A. Nossek Enhanced prediction of energy losses during adiabatic charging. [Citation Graph (0, 0)][DBLP ] Conf ] J. Zhou , R. M. Ziazadeh , H.-H. Ng , H.-T. Ng , David J. Allstot Charge-pump assisted low-power/low-voltage CMOS opamp design. [Citation Graph (0, 0)][DBLP ] Conf ] Detlev Schmitt , Terri S. Fiez A low voltage CMOS current source. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. E. P. van Engelen , Rudy J. van de Plassche New stability criteria for the design of low-pass sigma-delta modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Lapoe Lynn , Paul Ferguson Jr. A capacitor-based D/A converter with continuous time output for low-power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Massoud Pedram , Chih-Shun Ding Cycle-accurate macro-models for RT-level power analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhisa Ohnishi , Akihisa Yamada , Hiroaki Noda , Takashi Kambe A method of redundant clocking detection and power reduction at RT level design. [Citation Graph (0, 0)][DBLP ] Conf ] R. S. Bajwa , N. Schumann , H. Kojima Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Milind B. Kamble , Kanad Ghose Analytical energy dissipation models for low-power caches. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Meindl A history of low power electronics: how it began and where it's headed. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Frenkil Issues and directions in low power design tools: an industrial perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey System-level power estimation and optimization - challenges and perspectives. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Goel , Naresh R. Shanbhag Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong-Li He , Kai-Keung Chan , Chi-Ying Tsui , Ming L. Liou Low power motion estimation design using adaptive pixel truncation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Dong , K. Geoffrey Yung , William J. Kaiser Low power signal processing architectures for network microsensors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel K2: an estimator for peak sustainable power of VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] José C. Costa , José C. Monteiro , Srinivas Devadas Switching activity estimation using limited depth reconvergent path analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Marculescu , Diana Marculescu , Massoud Pedram Composite sequence compaction for finite-state machines using block entropy and high-order Markov models. [Citation Graph (0, 0)][DBLP ] Conf ] Toni Juan , Tomás Lang , Juan J. Navarro Reducing TLB power requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Musoll , Tomás Lang , Jordi Cortadella Exploiting the locality of memory references to reduce the address bus energy. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Kalambur , Mary Jane Irwin An extended addressing mode for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Fried Minimizing energy dissipation in high-speed multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung-Joon Kwon , Kwyro Lee A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications. [Citation Graph (0, 0)][DBLP ] Conf ] David Garrett , Mircea R. Stan Power reduction techniques for a spread spectrum based correlator. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Pen Yuan , Sung-Mo Kang A sequential procedure for average power analysis of sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. V. K. Pillai , Dhamin Al-Khalili , Asim J. Al-Khalili Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Hicks , Matthew Walnock , Robert Michael Owens Analysis of power consumption in memory hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Ying-Che Tseng , Steven C. Chin , Jason C. S. Woo The impact of SOI MOSFETs on low power digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Jin , Philip C. H. Chan , Mansun Chan On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter. [Citation Graph (0, 0)][DBLP ] Conf ] Markku Åberg , Anssi Leppänen , Arto Rantala , Jouko Marjonen Analogue LSI RF switch and beamforming matrixes for communications satellites. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Uno , Keiji Kumatani , Hiroyuki Okuhata , Isao Shirakawa , Toru Chiba Low power architecture for high speed infrared wireless communication system. [Citation Graph (0, 0)][DBLP ] Conf ] Mir Azam , Paul D. Franzon , Wentai Liu Low power data processing by elimination of redundant computations. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Yoshida , Bao-Yu Song , Hiroyuki Okuhata , Takao Onoye , Isao Shirakawa An object code compression approach to embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Unni Narayanan , Hon Wai Leong , Ki-Seok Chung , Chien-Liang Liu Low power multiplexer decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Winfried Nöth , Reiner Kolla Node normalization and decomposition in low power technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , Serge Pravossoudovitch , D. Severac A gate resizing technique for high reduction in power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Vuillod , Luca Benini , Giovanni De Micheli Re-mapping for low power under tight timing constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Burr , Anantha Chandrakasan , Fari Assaderaghi , Francky Catthoor , Frank Fox , Dave Greenhill , Deo Singh , Jim Sproch Low power design without compromise (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri A. Antoniadis SOI CMOS as a mainstream low power technology: a critical assessment. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa R. Banna , Philip C. H. Chan , Mansun Chan , Samuel K. H. Fung , Ping K. Ko Fully depleted CMOS/SOI device design guidelines for low power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Uming Ko , Andrew Pua , Anthony M. Hill , Pranjal Srivastava Hybrid dual-threshold design techniques for high-performance processors with low-power features. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Chen 0002 , Chenming Hu Device and technology optimizations for low power design in deep sub-micron regime. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Frank , Paul Solomon , Scott Reynolds , John Shin Supply and threshold voltage optimization for low power design. [Citation Graph (0, 0)][DBLP ] Conf ] Dragan Maksimovic , Vojin G. Oklobdzija , Borivoje Nikolic , K. Wayne Current Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Athas , Nestoras Tzartzanis , Lars J. Svensson , Lena Peterson , Huimin Li , Xing Yu Jiang , Peiqing Wang , W.-C. Liu AC-1: a clock-powered microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] 