Conferences in DBLP
Dan Dobberpuhl The design of a high performance low power microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] K. Bult , Amit Burstein , D. Chang , Michael J. Dong , M. Fielding , E. Kruglick , J. Ho , F. Lin , T. Lin , William J. Kaiser , H. Marcy , R. Mukai , Phyllis R. Nelson , F. Newburg , Kristofer S. J. Pister , Gregory J. Pottie , Henry Sanchez , Oscar M. Stafsudd , K. Tan , S. Xue , J. Yao Low power systems for wireless microsensors. [Citation Graph (0, 0)][DBLP ] Conf ] William H. Mangione-Smith , Phil Seong Ghang , Sean Nazareth , Paul Lettieri , Walt Boring , Rajeev Jain A low power architecture for wireless multimedia systems: lessons learned from building a power hog. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Landman High-level power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas L. Martin , Daniel P. Siewiorek A power metric for mobile systems. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh R. Shanbhag Lower bounds on power dissipation for DSP algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yamauchi , Toru Iwata , Hironori Akamatsu , Akira Matsuzawa A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras Tzartzanis , William C. Athas Energy recovery for the design of high-speed, low-power static RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroki Morimura , Nobutaro Shibata A 1-V 1-Mb SRAM for portable equipment. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Mike Tien-Chien Lee A novel methodology for transistor-level power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Pen Yuan , Chin-Chi Teng , Sung-Mo Kang Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Taku Uchino , Fumihiro Minami , Masami Murakata , Takashi Mitsuhashi Switching activity analysis for sequential circuits using Boolean approximation method. [Citation Graph (0, 0)][DBLP ] Conf ] Patrik Larsson , Chris J. Nicol Transition reduction in carry-save adder trees. [Citation Graph (0, 0)][DBLP ] Conf ] Lars E. Thon , Ghavam G. Shahidi , Werner Rausch , Gerald P. Coleman , Denny D. Tang , Dominic Schepis , Ronald Schulz , Fariborz Assadaraghi 250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Maitham Shams , Jo C. Ebergen , Mohamed I. Elmasry A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. [Citation Graph (0, 0)][DBLP ] Conf ] Uming Ko , Anthony M. Hill , Poras T. Balsara Design techniques for high performance, energy efficient control logic. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Athas , W.-C. Liu , Lars J. Svensson Energy-recovery CMOS for highly pipelined DSP designs. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Luca Benini , Giovanni De Micheli , Bruno Riccò Gate-level current waveform simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter H. Schneider , Shankar Krishnamoorthy Effects of correlations on accuracy of power analysis - an experimental study. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Ishihara , Hiroto Yasuura Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Katkoori , Ranga Vemuri Simulation based architectural power estimation for PLA-based controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Rabe , Wolfgang Nebel Short circuit power consumption of glitches. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Ma , Han-Bin Liang , Michael Kaneshiro , Carl Kyono , Robert Pryor , Ken Papworth , Sunny Cheng A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications. [Citation Graph (0, 0)][DBLP ] Conf ] L. Richard Carley , David F. Guillou , Suresh Santhanam Fabrication and performance of mesa interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] P. Lu , J. Ji , C. Chuang , L. Wagner , C. Hsieh , J. Kuang , L. Hsu , M. Pelella , S. Chu , C. Anderson Floating body effects in partially-depleted SOI CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amitava Chatterjee , Mahalingam Nandakumar , Ih-Chin Chen An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luis A. Plana , Steven M. Nowick Concurrency-oriented optimization for low-power asynchronous systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jui-Ming Chang , Massoud Pedram Energy minimization using multiple supply voltages. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , M. Burns , Gary D. Hachtel , Enrico Macii , H. Shin , Fabio Somenzi Symbolic computation of logic implications for technology-dependent low-power synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Ramsey W. Haddad Integrated resynthesis for low power. [Citation Graph (0, 0)][DBLP ] Conf ] James Burr , Laszlo Gal , Ramsey W. Haddad , Jan M. Rabaey , Bruce Wooley Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Koichiro Mashiko How to design low-power digital cellular phones. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , Olivier Coudert , Ramsey W. Haddad What is the state of the art in commercial EDA tools for low power? [Citation Graph (0, 0)][DBLP ] Conf ] Labros Bisdounis , Odysseas G. Koufopavlou , Spiridon Nikolaidis Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices. [Citation Graph (0, 0)][DBLP ] Conf ] Azeez J. Bhavnagarwala , Vivek De , Blanca Austin , James D. Meindl Circuit techniques for low-power CMOS GSI. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Chen 0002 , Yuhua Cheng , Chenming Hu Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. [Citation Graph (0, 0)][DBLP ] Conf ] R. V. K. Pillai , Dhamin Al-Khalili , Asim J. Al-Khalili Energy delay analysis of partial product reduction methods for parallel multiplier implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Nannarelli , Tomás Lang Low-power radix-4 divider. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin P. Acken , Mary Jane Irwin , Robert Michael Owens Power comparisons for barrel shifters. [Citation Graph (0, 0)][DBLP ] Conf ] Hirotsugu Kojima , Avadhani Shridhar Interlaced accumulation programming for low power DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Goel , Naresh R. Shanbhag Low-power adaptive filter architectures via strength reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Shivaling S. Mahant-Shetti , Carl Lemonds , Poras T. Balsara Leap frog multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas , Michele Quarantelli , J. Borel , Carlo Guardiani , G. Nicollini , G. Crisenza , Bruno Franzini , J. Wiart Manufacturability of low power CMOS technology solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Xinghai Tang , Vivek De , James D. Meindl Effects of random MOSFET parameter fluctuations on total power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] M. Eisele , Jörg Berthold , Doris Schmitt-Landsiedel , R. Mahnkopf The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Mercer , Larry Singer 12-b 125 MSPS CMOS D/A designed for spectral performance. [Citation Graph (0, 0)][DBLP ] Conf ] L. Grisoni , Alexandre Heubi , Peter Balsiger , Fausto Pellandini Implementation of a micro power 15-bit "floating-point" A/D converter. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Heubi , Peter Balsiger , Fausto Pellandini Micro power "relative precision" 13 bits cyclic RSD A/D converter. [Citation Graph (0, 0)][DBLP ] Conf ] Marios C. Papaefthymiou , Kumar N. Lalgudi Fixed-phase retiming for low power design. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Vuillod , Luca Benini , Alessandro Bogliolo , Giovanni De Micheli Clock skew optimization for peak current reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Cheng-Kok Koh , Kwok-Shing Leung Simultaneous buffer and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Domine Leenaerts , G. H. M. Joordens , J. A. Hegt A low power high performance switched-current multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Fried , Ziv Azmanov Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management. [Citation Graph (0, 0)][DBLP ] Conf ] Fan You , Sherif H. K. Embabi , Edgar Sánchez-Sinencio A 1.5V class AB output buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Nikil D. Dutt Low-power mapping of behavioral arrays to multiple memories. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher K. Lennard , Premal Buch , A. Richard Newton Logic synthesis using power-sensitive don't care sets. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan , Mitrajit Chatterjee , Madhu V. Swarna , Wolfgang Kunz Gate-level synthesis for low-power using new transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi Controller re-specification to minimize switching activity in controller/data path circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Qiuting Huang , Philipp Basedau A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm. [Citation Graph (0, 0)][DBLP ] Conf ] Tadahiro Kuroda , Tetsuya Fujita , Shinji Mita , Toshiaki Mori , Kenji Matsuo , Masakazu Kakumu , Takayasu Sakurai Substrate noise influence on circuit performance in variable threshold-voltage scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Gu-Yeon Wei , Mark Horowitz A low power switching power supply for self-clocked systems. [Citation Graph (0, 0)][DBLP ] Conf ] Godi Fischer , James C. Daly , Chun Yang , Conrad W. Recksiek , Kevin D. Friedland Design of a programmable temperature monitoring device for tagging small fish. [Citation Graph (0, 0)][DBLP ] Conf ] Akhilesh Tyagi Entropic bounds on FSM switching. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevamurty Nemani , Farid N. Najm High-level power estimation and the area complexity of Boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] Mircea R. Stan , Wayne P. Burleson Two dimensional codes for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Llopis , Manoj Sachdev Low power, testable dual edge triggered flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan , Vadim Gutnik , Thucydides Xanthopoulos Data driven signal processing: an approach for energy efficient computing. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuru Hiraki , Raminder Singh Bajwa , Hirotsugu Kojima , Douglas J. Gorny , Ken-ichi Nitta , Avadhani Shridhar , Katsuro Sasaki , Koichi Seki Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Wuytack , Francky Catthoor , Lode Nachtergaele , Hugo De Man Power exploration for data dominated video applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kerry Bernstein , John E. Bertsch , William F. Clark , John J. Ellis-Monaghan , Larry G. Heller , Edward J. Nowak Practical performance/power alternatives within an existing CMOS technology generation. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek De , James D. Meindl A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). [Citation Graph (0, 0)][DBLP ] Conf ] David J. Frank Comparison of high speed voltage-scaled conventional and adiabatic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ram K. Krishnamurthy , Ihor Lys , L. Richard Carley Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. [Citation Graph (0, 0)][DBLP ] Conf ] 