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Conferences in DBLP

International Symposium on Low Power Electronics and Design (islped)
1996 (conf/islped/1996)

  1. Dan Dobberpuhl
    The design of a high performance low power microprocessor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:11-16 [Conf]
  2. K. Bult, Amit Burstein, D. Chang, Michael J. Dong, M. Fielding, E. Kruglick, J. Ho, F. Lin, T. Lin, William J. Kaiser, H. Marcy, R. Mukai, Phyllis R. Nelson, F. Newburg, Kristofer S. J. Pister, Gregory J. Pottie, Henry Sanchez, Oscar M. Stafsudd, K. Tan, S. Xue, J. Yao
    Low power systems for wireless microsensors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:17-21 [Conf]
  3. William H. Mangione-Smith, Phil Seong Ghang, Sean Nazareth, Paul Lettieri, Walt Boring, Rajeev Jain
    A low power architecture for wireless multimedia systems: lessons learned from building a power hog. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:23-28 [Conf]
  4. Paul E. Landman
    High-level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:29-35 [Conf]
  5. Thomas L. Martin, Daniel P. Siewiorek
    A power metric for mobile systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:37-42 [Conf]
  6. Naresh R. Shanbhag
    Lower bounds on power dissipation for DSP algorithms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:43-48 [Conf]
  7. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
    A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:49-54 [Conf]
  8. Nestoras Tzartzanis, William C. Athas
    Energy recovery for the design of high-speed, low-power static RAMs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:55-60 [Conf]
  9. Hiroki Morimura, Nobutaro Shibata
    A 1-V 1-Mb SRAM for portable equipment. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:61-66 [Conf]
  10. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
    A novel methodology for transistor-level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:67-72 [Conf]
  11. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:73-78 [Conf]
  12. Taku Uchino, Fumihiro Minami, Masami Murakata, Takashi Mitsuhashi
    Switching activity analysis for sequential circuits using Boolean approximation method. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:79-84 [Conf]
  13. Patrik Larsson, Chris J. Nicol
    Transition reduction in carry-save adder trees. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:85-88 [Conf]
  14. Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi
    250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:89-92 [Conf]
  15. Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry
    A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:93-96 [Conf]
  16. Uming Ko, Anthony M. Hill, Poras T. Balsara
    Design techniques for high performance, energy efficient control logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:97-100 [Conf]
  17. William C. Athas, W.-C. Liu, Lars J. Svensson
    Energy-recovery CMOS for highly pipelined DSP designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:101-104 [Conf]
  18. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level current waveform simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:109-112 [Conf]
  19. Peter H. Schneider, Shankar Krishnamoorthy
    Effects of correlations on accuracy of power analysis - an experimental study. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:113-116 [Conf]
  20. Tohru Ishihara, Hiroto Yasuura
    Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:117-120 [Conf]
  21. Srinivas Katkoori, Ranga Vemuri
    Simulation based architectural power estimation for PLA-based controllers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:121-124 [Conf]
  22. Dirk Rabe, Wolfgang Nebel
    Short circuit power consumption of glitches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:125-128 [Conf]
  23. Jun Ma, Han-Bin Liang, Michael Kaneshiro, Carl Kyono, Robert Pryor, Ken Papworth, Sunny Cheng
    A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:129-132 [Conf]
  24. L. Richard Carley, David F. Guillou, Suresh Santhanam
    Fabrication and performance of mesa interconnect. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:133-137 [Conf]
  25. P. Lu, J. Ji, C. Chuang, L. Wagner, C. Hsieh, J. Kuang, L. Hsu, M. Pelella, S. Chu, C. Anderson
    Floating body effects in partially-depleted SOI CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:139-144 [Conf]
  26. Amitava Chatterjee, Mahalingam Nandakumar, Ih-Chin Chen
    An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:145-150 [Conf]
  27. Luis A. Plana, Steven M. Nowick
    Concurrency-oriented optimization for low-power asynchronous systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:151-156 [Conf]
  28. Jui-Ming Chang, Massoud Pedram
    Energy minimization using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:157-162 [Conf]
  29. R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
    Symbolic computation of logic implications for technology-dependent low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:163-168 [Conf]
  30. Olivier Coudert, Ramsey W. Haddad
    Integrated resynthesis for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:169-174 [Conf]
  31. James Burr, Laszlo Gal, Ramsey W. Haddad, Jan M. Rabaey, Bruce Wooley
    Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel). [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:175- [Conf]
  32. Koichiro Mashiko
    How to design low-power digital cellular phones. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:177-180 [Conf]
  33. Kurt Keutzer, Olivier Coudert, Ramsey W. Haddad
    What is the state of the art in commercial EDA tools for low power? [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:181-187 [Conf]
  34. Labros Bisdounis, Odysseas G. Koufopavlou, Spiridon Nikolaidis
    Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:189-192 [Conf]
  35. Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
    Circuit techniques for low-power CMOS GSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:193-196 [Conf]
  36. Kai Chen 0002, Yuhua Cheng, Chenming Hu
    Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:197-200 [Conf]
  37. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Energy delay analysis of partial product reduction methods for parallel multiplier implementation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:201-204 [Conf]
  38. Alberto Nannarelli, Tomás Lang
    Low-power radix-4 divider. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:205-208 [Conf]
  39. Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
    Power comparisons for barrel shifters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:209-212 [Conf]
  40. Hirotsugu Kojima, Avadhani Shridhar
    Interlaced accumulation programming for low power DSP. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:213-216 [Conf]
  41. Manish Goel, Naresh R. Shanbhag
    Low-power adaptive filter architectures via strength reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:217-220 [Conf]
  42. Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara
    Leap frog multiplier. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:221-223 [Conf]
  43. Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, G. Nicollini, G. Crisenza, Bruno Franzini, J. Wiart
    Manufacturability of low power CMOS technology solutions. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:225-232 [Conf]
  44. Xinghai Tang, Vivek De, James D. Meindl
    Effects of random MOSFET parameter fluctuations on total power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:233-236 [Conf]
  45. M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf
    The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:237-242 [Conf]
  46. Douglas Mercer, Larry Singer
    12-b 125 MSPS CMOS D/A designed for spectral performance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:243-246 [Conf]
  47. L. Grisoni, Alexandre Heubi, Peter Balsiger, Fausto Pellandini
    Implementation of a micro power 15-bit "floating-point" A/D converter. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:247-252 [Conf]
  48. Alexandre Heubi, Peter Balsiger, Fausto Pellandini
    Micro power "relative precision" 13 bits cyclic RSD A/D converter. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:253-257 [Conf]
  49. Marios C. Papaefthymiou, Kumar N. Lalgudi
    Fixed-phase retiming for low power design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:259-264 [Conf]
  50. Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Clock skew optimization for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:265-270 [Conf]
  51. Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
    Simultaneous buffer and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:271-276 [Conf]
  52. Domine Leenaerts, G. H. M. Joordens, J. A. Hegt
    A low power high performance switched-current multiplier. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:277-280 [Conf]
  53. Rafael Fried, Ziv Azmanov
    Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:281-284 [Conf]
  54. Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
    A 1.5V class AB output buffer. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:285-288 [Conf]
  55. Preeti Ranjan Panda, Nikil D. Dutt
    Low-power mapping of behavioral arrays to multiple memories. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:289-292 [Conf]
  56. Christopher K. Lennard, Premal Buch, A. Richard Newton
    Logic synthesis using power-sensitive don't care sets. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:293-296 [Conf]
  57. Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
    Gate-level synthesis for low-power using new transformations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:297-300 [Conf]
  58. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller re-specification to minimize switching activity in controller/data path circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:301-304 [Conf]
  59. Qiuting Huang, Philipp Basedau
    A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:305-308 [Conf]
  60. Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai
    Substrate noise influence on circuit performance in variable threshold-voltage scheme. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:309-312 [Conf]
  61. Gu-Yeon Wei, Mark Horowitz
    A low power switching power supply for self-clocked systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:313-317 [Conf]
  62. Godi Fischer, James C. Daly, Chun Yang, Conrad W. Recksiek, Kevin D. Friedland
    Design of a programmable temperature monitoring device for tagging small fish. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:319-322 [Conf]
  63. Akhilesh Tyagi
    Entropic bounds on FSM switching. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:323-328 [Conf]
  64. Mahadevamurty Nemani, Farid N. Najm
    High-level power estimation and the area complexity of Boolean functions. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:329-334 [Conf]
  65. Mircea R. Stan, Wayne P. Burleson
    Two dimensional codes for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:335-340 [Conf]
  66. Rafael Llopis, Manoj Sachdev
    Low power, testable dual edge triggered flip-flops. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:341-345 [Conf]
  67. Anantha Chandrakasan, Vadim Gutnik, Thucydides Xanthopoulos
    Data driven signal processing: an approach for energy efficient computing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:347-352 [Conf]
  68. Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
    Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:353-358 [Conf]
  69. Sven Wuytack, Francky Catthoor, Lode Nachtergaele, Hugo De Man
    Power exploration for data dominated video applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:359-364 [Conf]
  70. Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak
    Practical performance/power alternatives within an existing CMOS technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:365-370 [Conf]
  71. Vivek De, James D. Meindl
    A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:371-375 [Conf]
  72. David J. Frank
    Comparison of high speed voltage-scaled conventional and adiabatic circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:377-380 [Conf]
  73. Ram K. Krishnamurthy, Ihor Lys, L. Richard Carley
    Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:381-386 [Conf]
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NOTICE2
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