Conferences in DBLP
Jan M. Rabaey Wireless beyond the third generation wireless beyond the third generation: facing the energy challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Baruch Solomon , Avi Mendelson , Doron Orenstein , Yoav Almog , Ronny Ronen Micro-operation cache: a power aware frontend for the variable instruction length ISA. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Huang , Jose Renau , Seung-Moon Yoo , Josep Torrellas L1 data cache decomposition for energy efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Amirali Baniasadi , Andreas Moshovos Instruction flow-based front-end throttling for power-aware high-performance processors. [Citation Graph (0, 0)][DBLP ] Conf ] Vasily G. Moshnyaga Energy reduction in queues and stacks by adaptive bitwidth compression. [Citation Graph (0, 0)][DBLP ] Conf ] Johan A. Pouwelse , Koen Langendoen , Henk J. Sips Energy priority scheduling for variable voltage processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chaeseok Im , Huiseok Kim , Soonhoi Ha Dynamic voltage scheduling technique for low-power multimedia applications using buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Han-Saem Yun , Jihong Kim Power-aware modulo scheduling for high-performance VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Flavius Gruian Hard real-time scheduling for low-energy using stochastic data and DVS processors. [Citation Graph (0, 0)][DBLP ] Conf ] Dejan Markovic , Borivoje Nikolic , Robert W. Brodersen Analysis and design of low-energy flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Hoang Q. Dao , Kevin J. Nowka , Vojin G. Oklobdzija Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. [Citation Graph (0, 0)][DBLP ] Conf ] Soontae Kim , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Anand Sivasubramaniam , Mary Jane Irwin , E. Geethanjali Power-aware partitioned cache architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Atila Alvandpour , Ram Krishnamurthy , K. Soumyanath , Shekhar Borkar A low-leakage dynamic multi-ported register file in 0.13mm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yang , Rajiv Gupta Energy-efficient load and store reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , J. Ramanujam , Ugur Sezer Compiler support for block buffering. [Citation Graph (0, 0)][DBLP ] Conf ] Eui-Young Chung , Luca Benini , Giovanni De Micheli Automatic source code specialization for energy reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yang , Rajiv Gupta FV encoding for low-power data I/O. [Citation Graph (0, 0)][DBLP ] Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula Time-to-failure estimation for batteries in portable electronic systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vlasios Tsiatsis , Scott Zimbeck , Mani B. Srivastava Architecture strategies for energy-efficient packet forwarding in wireless sensor networks. [Citation Graph (0, 0)][DBLP ] Conf ] Curt Schurgers , Olivier Aberthorne , Mani B. Srivastava Modulation scaling for Energy Aware Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Belady Cooling and power consideration for semiconductors into the next century. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wang , Seong-Hwan Cho , Charles Sodini , Anantha Chandrakasan Energy efficient Modulation and MAC for Asymmetric RF Microsensor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Song Ye , Koji Yano , C. Andre T. Salama 1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Mostafa , Sherif H. K. Embabi , Mostafa Elmala A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunsik Im , T. Inukai , H. Gomyo , T. Hiramoto , T. Sakurai VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaobo Fan , Carla Schlatter Ellis , Alvin R. Lebeck Memory controller policies for DRAM power management. [Citation Graph (0, 0)][DBLP ] Conf ] Russ Joseph , Margaret Martonosi Run-time power estimation in high performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Stanley-Marbell , Michael S. Hsiao Fast, flexible, cycle-accurate energy estimation. [Citation Graph (0, 0)][DBLP ] Conf ] James Tschanz , Siva Narendra , Zhanping Chen , Shekhar Borkar , Manoj Sachdev , Vivek De Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Joong-Seok Moon , William C. Athas , Peter A. Beerel Theory and practical implementation of harmonic resonant rail driver. [Citation Graph (0, 0)][DBLP ] Conf ] Conrad H. Ziesler , Suhwan Kim , Marios C. Papaefthymiou A resonant clock generator for single-phase adiabatic systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen V. Kosonocky , Michael Immediato , Peter E. Cottrell , Terence B. Hook , Randy W. Mann , Jeff Brown Enchanced multi-threshold (MTCMOS) circuits using variable well bias. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo Encodings for high-performance for energy-efficient signaling. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Macchiarulo , Enrico Macii , Massimo Poncino Low-energy for deep-submicron address buses. [Citation Graph (0, 0)][DBLP ] Conf ] Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram Irredundant address bus encoding for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mamidipaka , Daniel S. Hirschberg , Nikil Dutt Low power address encoding using self-organizing lists. [Citation Graph (0, 0)][DBLP ] Conf ] Deborah Estrin Wireless sensor networks: application driver for low power distributed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Siva Narendra , Vivek De , Dimitri Antoniadis , Anantha Chandrakasan , Shekhar Borkar Scaling of stack effect and its application for leakage reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Inukai , Toshiro Hiramoto , Takayasu Sakurai Variable threshold CMOS (VTCMOS) in series connected circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Keshavarzi , Sean Ma , Siva Narendra , B. Bloechel , K. Mistry , T. Ghani , Shekhar Borkar , Vivek De Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Rongtian Zhang , Kaushik Roy , David B. Janes Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid , Ann Gordon-Ross A self-optimizing embedded microprocessor using a loop table for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Daehong Kim , Dongwan Shin , Kiyoung Choi Low power pipelining of linear systems: a common operand centric approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yun Cao , Hiroto Yasuura A system-level energy minimization approach using datapath width optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Gurhan Kucuk , Kanad Ghose , Dmitry Ponomarev , Peter M. Kogge Energy: efficient instruction dispatch buffer design for superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tirdad Sowlati , Vickram Vathulya , Domine Leenaerts High density capacitance structures in submicron CMOS for low power RF application. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Mostafa , Mourad N. El-Gamal A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applications. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Chien , Igor Elgorriaga , Charles McConaghy Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networks. [Citation Graph (0, 0)][DBLP ] Conf ] Vjekoslav Svilan , James B. Burr , G. Tyler Effects of elevated temperature on tunable near-zero threshold CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Fujii , Takakuni Douseki , Yuichi Kado A sub-1V dual-threshold domino circuit using product-of-sum logic. [Citation Graph (0, 0)][DBLP ] Conf ] W. Chen , Wei Hwang , P. Kudva , George Gristede , Stephen V. Kosonocky , Rajiv V. Joshi Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Naran Sirisantana , Aiqun Cao , Shawn Davidson , Cheng-Kok Koh , Kaushik Roy Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkun Shin , Jihong Kim A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Hsing Hsu , Ulrich Kremer , Michael S. Hsiao Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Manzak , Chaitali Chakrabarti Variable voltage task scheduling algorithms for minimizing energy. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Hirabayashi , Koichi Nose , Takayasu Sakurai Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. [Citation Graph (0, 0)][DBLP ] Conf ] Mario R. Casu , Gianluca Piccinini , Guido Masera , Maurizio Zamboni Synthesis of low-leakage PD-SOI circuits with body-biasing. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , L. Richard Carley , Roberto Zafalon , Nicola Dragone Low-power technology mapping for mixed-swing logic. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Bodapati , Farid N. Najm Frequency-domain supply current macro-model. [Citation Graph (0, 0)][DBLP ] Conf ] Rola A. Baki , Mourad N. El-Gamal A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Fukumoto , Hiroyuki Okada , Kazuyuki Nakamura Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations. [Citation Graph (0, 0)][DBLP ] Conf ] Louis S. Y. Wong , Shohan Hossain , Andre Walker Leakage current cancellation technique for low power switched-capacitor circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Bo Cho , Alexander Krymski , Eric R. Fossum A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Alberto Nannarelli Cached-code compression for energy minimization in embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] David Garrett , Bing Xu , Chris Nicol Energy efficient turbo decoding for 3G mobile. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Wang , Naresh R. Shanbhag Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Talpes , Diana Marculescu Power reduction through work reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , D. Meltzer Clocking strategies and scannable latches for low power appliacations. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung-il Kim , Kaushik Roy Ultra-low power DLMS adaptive filter for hearing aid applications. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Miura , Kazushige Ayukawa , Takao Watanabe A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. [Citation Graph (0, 0)][DBLP ] Conf ] Paul-Peter Sotiriadis , Theodoros Konstantakopoulos , Anantha Chandrakasan Analysis and implementation of charge recycling for deep sub-micron buses. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Takayasu Sakurai Estimation of power distribution in VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar Bobba , Ibrahim N. Hajj Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Park , Andreas Savvides , Mani B. Srivastava Battery capacity measurement and analysis using lithium coin cell battery. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendran Panda , Savithri Sundareswaran , David Blaauw On the interaction of power distribution network with substrate. [Citation Graph (0, 0)][DBLP ] Conf ] 