Conferences in DBLP
Bryan D. Ackland , Chris Nicol High performance DSPs - what's hot and what's not? [Citation Graph (0, 0)][DBLP ] Conf ] Christer Svensson , Atila Alvandpour Low power and low voltage CMOS digital circuit techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Hsien Lin , Henry Sanchez , Razieh Rofougaran , William J. Kaiser CMOS front end components for micropower RF wireless systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tamara I. Ahrens , Thomas H. Lee A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Knapp , Wilhelm Wilhelm , Mira Rest , Hans-Peter Trost A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-hong Chen , Chi-Ying Tsui Towards the capability of providing power-area-delay trade-off at the register transfer level. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Macii , Enrico Macii , Massimo Poncino , Riccardo Scarsi Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Radu Marculescu , Massoud Pedram Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Y. Chou , A. J. Budrys , Kit M. Cham Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Miyazaki , Hiroyuki Mizuno , Koichiro Ishibashi A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] S. J. Abou-Samra , P. A. Aisa , Alain Guyot , Bernard Courtois 3D CMOS SOL for high performance computing. [Citation Graph (0, 0)][DBLP ] Conf ] Joonho Gil , Minkyu Je , Jongho Lee , Hyungcheol Shin A high speed and low power SOL inverter using active body-bias. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , Gianluca Albera , Srilatha Manne Power and performance tradeoffs using various caching strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim N. Hajj , George D. Stamoulis , Nikolaos Bellas , Constantine D. Polychronopoulos Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor Pering , Thomas D. Burd , Robert W. Brodersen The simulation and evaluation of dynamic voltage scaling algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Taku Ohsawa , Koji Kai , Kazuaki Murakami Optimizing the DRAM refresh count for merged DRAM/logic LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinand Sluijs , Kees Hart , Wouter Groeneveld , Stephan Haag Integrated DC/DC converter with digital controller. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael J. Betancourt-Zamora , Thomas H. Lee CMOS VCOs for frequency synthesis in wireless biotelemetry. [Citation Graph (0, 0)][DBLP ] Conf ] Gareth Keane , Jonathan Spanier , Roger Woods The impact of data characteristics and hardware topology on hardware selection for low power DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Mircea R. Stan Low threshold CMOS circuits with low standby current. [Citation Graph (0, 0)][DBLP ] Conf ] Azeez J. Bhavnagarwala , Blanca Austin , James D. Meindl Minimum supply voltage for bulk Si CMOS GSI. [Citation Graph (0, 0)][DBLP ] Conf ] Volker Dudek , Reinhard Grube , Bernd Höfflinger , Michael Schau 0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology. [Citation Graph (0, 0)][DBLP ] Conf ] L. Richard Carley , Akshay Aggarwal , Ram K. Krishnamurthy Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Nannarelli , Tomás Lang Power-delay tradeoffs for radix-4 and radix-8 dividers. [Citation Graph (0, 0)][DBLP ] Conf ] Mauro Chinosi , Roberto Zafalon , Carlo Guardiani Automatic characterization and modeling of power consumption in static RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Shun Ding , Cheng-Ta Hsieh , Massoud Pedram Improving sampling efficiency for system level power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Dragone , Roberto Zafalon , Carlo Guardiani , Cristina Silvano Power invariant vector compaction based on bit clustering and temporal partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys , Robert J. Gebotys An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jay Abraham Power calculation and modeling in deep submicron. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Soo-Ik Chae , Kiyoung Choi Partial bus-invert coding for power optimization of system level bus. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Peset Llopis , Kees G. W. Goossens The petrol approach to high-level power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Won Namgoong , Teresa H. Y. Meng Power consumption of parallel spread spectrum correlator architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Uzi Zangi , Ran Ginosar A low power video processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail , Eby G. Friedman , José Luis Neves Power dissipated by CMOS gates driving lossless transmission lines. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Abhijit Dharchoudhury , Rajendran Panda , Supamas Sirichotiyakul , Chanhee Oh , Tim Edwards Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques C. Rudell , Jia-Jiunn Ou , R. Sekhar Narayanaswami , George Chien , Jeffrey A. Weldon , Li Lin , King-Chun Tsai , Luns Tee , Kelvin Khoo , Danelle Au , Troy Robinson , Danilo Gerna , Masanori Otsuka , Paul R. Gray Recent developments in high integration multi-standard CMOS transceivers for personal communication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Kusse , Jan M. Rabaey Low-energy embedded FPGA structures. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Zhang , Jan M. Rabaey Low-swing interconnect interface circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Suhwan Kim , Marios C. Papaefthymiou True single-phase energy-recovering logic for low-power, high-speed VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Robin Hodgson , Polly Siegel System-level power estimation and optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sari L. Coumeri , Donald E. Thomas Memory modeling for system synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alessandro Bogliolo , Stefano Cavallucci , Bruno Riccò Monitoring system activity for OS-directed dynamic power management. [Citation Graph (0, 0)][DBLP ] Conf ] Abram P. Dancy , Anantha Chandrakasan A reconfigurable dual output low power digital PWM power converter. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Ishihara , Hiroto Yasuura Voltage scheduling problem for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Burger , Qiuting Huang On the optimum design of regulated cascode operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Unni Narayanan , Peichen Pan , C. L. Liu Low power logic synthesis under a general delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Seok Chung , C. L. Liu Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Stojanovic , Vojin G. Oklobdzija , Raminder Singh Bajwa A unified approach in the analysis of latches and flip-flops for low-power systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Min Jiang , Kwang-Ting Cheng , An-Chang Deng Estimation of maximum power supply noise for deep sub-micron designs. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. [Citation Graph (0, 0)][DBLP ] Conf ] Atila Alvandpour , Per Larsson-Edefors , Christer Svensson Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj Decorrelating (DECOR) transformations for low-power adaptive filters. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Sacha , Mary Jane Irwin The logarithmic number system for strength reduction in adaptive filtering. [Citation Graph (0, 0)][DBLP ] Conf ] David Garrett , Mircea R. Stan Low power architecture of the soft-output Viterbi algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] J. Patrick Brennan , Alvar Dean , Stephan Kenyon , Sebastian Ventrone Low power methodology and design techniques for processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Benoit , Sandy Taylor , David Overhauser , Steffen Rochel Power distribution in high-performance design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Bolotski , Phillip Alvelda Low-power miniaturized information display systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jinn-Shyan Wang , Po-Hui Yang , Wayne Tseng Low-power embedded SRAM macros with current-mode read/write operations. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Avery , Marwan A. Jabri A three-port adiabatic register file suitable for embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Nii , Hiroshi Makino , Yoshiki Tujihashi , Chikayoshi Morishima , Yasushi Hayakawa , Hiroyuki Nunogami , Takahiko Arakawa , Hisanori Hamano A low power SRAM using auto-backgate-controlled MT-CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha Fast high-level power estimation for control-flow intensive design. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , Peter M. Kogge The energy complexity of register files. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Leao da Silva Jr. , Francky Catthoor , Diederik Verkest , Hugo De Man Power exploration for dynamic data types through virtual memory management refinement. [Citation Graph (0, 0)][DBLP ] Conf ] 