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Conferences in DBLP

International Symposium on Low Power Electronics and Design (islped)
1998 (conf/islped/1998)

  1. Bryan D. Ackland, Chris Nicol
    High performance DSPs - what's hot and what's not? [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:1-6 [Conf]
  2. Christer Svensson, Atila Alvandpour
    Low power and low voltage CMOS digital circuit techniques. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:7-10 [Conf]
  3. Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser
    CMOS front end components for micropower RF wireless systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:11-15 [Conf]
  4. Tamara I. Ahrens, Thomas H. Lee
    A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:16-19 [Conf]
  5. Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost
    A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:20-23 [Conf]
  6. Chun-hong Chen, Chi-Ying Tsui
    Towards the capability of providing power-area-delay trade-off at the register transfer level. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:24-29 [Conf]
  7. Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:30-35 [Conf]
  8. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:36-41 [Conf]
  9. Eric Y. Chou, A. J. Budrys, Kit M. Cham
    Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:42-47 [Conf]
  10. Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi
    A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:48-53 [Conf]
  11. S. J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois
    3D CMOS SOL for high performance computing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:54-58 [Conf]
  12. Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin
    A high speed and low power SOL inverter using active body-bias. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:59-63 [Conf]
  13. R. Iris Bahar, Gianluca Albera, Srilatha Manne
    Power and performance tradeoffs using various caching strategies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:64-69 [Conf]
  14. Ibrahim N. Hajj, George D. Stamoulis, Nikolaos Bellas, Constantine D. Polychronopoulos
    Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:70-75 [Conf]
  15. Trevor Pering, Thomas D. Burd, Robert W. Brodersen
    The simulation and evaluation of dynamic voltage scaling algorithms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:76-81 [Conf]
  16. Taku Ohsawa, Koji Kai, Kazuaki Murakami
    Optimizing the DRAM refresh count for merged DRAM/logic LSIs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:82-87 [Conf]
  17. Ferdinand Sluijs, Kees Hart, Wouter Groeneveld, Stephan Haag
    Integrated DC/DC converter with digital controller. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:88-90 [Conf]
  18. Rafael J. Betancourt-Zamora, Thomas H. Lee
    CMOS VCOs for frequency synthesis in wireless biotelemetry. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:91-94 [Conf]
  19. Gareth Keane, Jonathan Spanier, Roger Woods
    The impact of data characteristics and hardware topology on hardware selection for low power DSP. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:94-96 [Conf]
  20. Mircea R. Stan
    Low threshold CMOS circuits with low standby current. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:97-99 [Conf]
  21. Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
    Minimum supply voltage for bulk Si CMOS GSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:100-102 [Conf]
  22. Volker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau
    0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:103-105 [Conf]
  23. L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy
    Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:106-108 [Conf]
  24. Alberto Nannarelli, Tomás Lang
    Power-delay tradeoffs for radix-4 and radix-8 dividers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:109-111 [Conf]
  25. Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
    Automatic characterization and modeling of power consumption in static RAMs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:112-114 [Conf]
  26. Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
    Improving sampling efficiency for system level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:115-117 [Conf]
  27. Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano
    Power invariant vector compaction based on bit clustering and temporal partitioning. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:118-120 [Conf]
  28. Catherine H. Gebotys, Robert J. Gebotys
    An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:121-123 [Conf]
  29. Jay Abraham
    Power calculation and modeling in deep submicron. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:124-126 [Conf]
  30. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of system level bus. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:127-129 [Conf]
  31. Rafael Peset Llopis, Kees G. W. Goossens
    The petrol approach to high-level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:130-132 [Conf]
  32. Won Namgoong, Teresa H. Y. Meng
    Power consumption of parallel spread spectrum correlator architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:133-135 [Conf]
  33. Uzi Zangi, Ran Ginosar
    A low power video processor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:136-138 [Conf]
  34. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Power dissipated by CMOS gates driving lossless transmission lines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:139-142 [Conf]
  35. David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
    Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:143-148 [Conf]
  36. Jacques C. Rudell, Jia-Jiunn Ou, R. Sekhar Narayanaswami, George Chien, Jeffrey A. Weldon, Li Lin, King-Chun Tsai, Luns Tee, Kelvin Khoo, Danelle Au, Troy Robinson, Danilo Gerna, Masanori Otsuka, Paul R. Gray
    Recent developments in high integration multi-standard CMOS transceivers for personal communication systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:149-154 [Conf]
  37. Eric Kusse, Jan M. Rabaey
    Low-energy embedded FPGA structures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:155-160 [Conf]
  38. Hui Zhang, Jan M. Rabaey
    Low-swing interconnect interface circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:161-166 [Conf]
  39. Suhwan Kim, Marios C. Papaefthymiou
    True single-phase energy-recovering logic for low-power, high-speed VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:167-172 [Conf]
  40. Luca Benini, Robin Hodgson, Polly Siegel
    System-level power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:173-178 [Conf]
  41. Sari L. Coumeri, Donald E. Thomas
    Memory modeling for system synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:179-184 [Conf]
  42. Luca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò
    Monitoring system activity for OS-directed dynamic power management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:185-190 [Conf]
  43. Abram P. Dancy, Anantha Chandrakasan
    A reconfigurable dual output low power digital PWM power converter. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:191-196 [Conf]
  44. Tohru Ishihara, Hiroto Yasuura
    Voltage scheduling problem for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:197-202 [Conf]
  45. Thomas Burger, Qiuting Huang
    On the optimum design of regulated cascode operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:203-208 [Conf]
  46. Unni Narayanan, Peichen Pan, C. L. Liu
    Low power logic synthesis under a general delay model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:209-214 [Conf]
  47. Ki-Seok Chung, C. L. Liu
    Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:215-220 [Conf]
  48. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:221-226 [Conf]
  49. Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
    A unified approach in the analysis of latches and flip-flops for low-power systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:227-232 [Conf]
  50. Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
    Estimation of maximum power supply noise for deep sub-micron designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:233-238 [Conf]
  51. Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
    Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:239-244 [Conf]
  52. Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
    Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:245-249 [Conf]
  53. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
    Decorrelating (DECOR) transformations for low-power adaptive filters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:250-255 [Conf]
  54. John R. Sacha, Mary Jane Irwin
    The logarithmic number system for strength reduction in adaptive filtering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:256-261 [Conf]
  55. David Garrett, Mircea R. Stan
    Low power architecture of the soft-output Viterbi algorithm. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:262-267 [Conf]
  56. J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone
    Low power methodology and design techniques for processor design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:268-273 [Conf]
  57. Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel
    Power distribution in high-performance design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:274-278 [Conf]
  58. Michael Bolotski, Phillip Alvelda
    Low-power miniaturized information display systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:279-281 [Conf]
  59. Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng
    Low-power embedded SRAM macros with current-mode read/write operations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:282-287 [Conf]
  60. Stephan Avery, Marwan A. Jabri
    A three-port adiabatic register file suitable for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:288-292 [Conf]
  61. Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
    A low power SRAM using auto-backgate-controlled MT-CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:293-298 [Conf]
  62. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Fast high-level power estimation for control-flow intensive design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:299-304 [Conf]
  63. Victor V. Zyuban, Peter M. Kogge
    The energy complexity of register files. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:305-310 [Conf]
  64. Julio Leao da Silva Jr., Francky Catthoor, Diederik Verkest, Hugo De Man
    Power exploration for dynamic data types through virtual memory management refinement. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:311-316 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
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