Conferences in DBLP
A. A. Abidi , Houshang Darabi Low power RF integrated circuits: principles and practice. [Citation Graph (0, 0)][DBLP ] Conf ] Finn Müller , Nikolai Bisgaard , John Melanson Algorithm and architecture of a 1V low power hearing instrument DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroki Morimura , Satoshi Shigematsu , Shinsuke Konaka A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras Tzartzanis , William C. Athas Retractile clock-powered logic. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Balamurugan , Naresh R. Shanbhag Energy-efficient dynamic circuit design in the presence of crosstalk noise. [Citation Graph (0, 0)][DBLP ] Conf ] Rajamohana Hegde , Naresh R. Shanbhag Energy-efficient signal processing via algorithmic noise-tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Yuk-Hang Leung , Chung-Wai Yue , Chi-Ying Tsui , Roger S. Cheng Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Deng , Charles Chien A low energy architecture for fast PN acquisition. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Meninger , Jose Oscar Mur-Miranda , Rajeevan Amirtharajah , Anantha Chandrakasan , Jeffrey Lang Vibration-to-electric energy conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Fuyuki Ichiba , Kojiro Suzuki , Shinji Mita , Tadahiro Kuroda , Tohru Furuyama Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Koifman , Yachin Afek , Joseph Shor Circuit methods for the integration of low voltage (1.1-1.8V) analog functions on system-on-a-chip IC's in a single-poly CMOS processes. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Bellas , Ibrahim N. Hajj , Constantine D. Polychronopoulos Using dynamic cache management techniques to reduce energy in a high-performance processor. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Milind B. Kamble Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Curt Schurgers , Francky Catthoor , Marc Engels Energy efficient data transfer and storage organization for a MAP turbo decoder module. [Citation Graph (0, 0)][DBLP ] Conf ] Bharath Ramasubramanian , Herman Schmit , L. Richard Carley Mixed-swing quadrail for low power dual-rail domino logic. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Bishop , Mary Jane Irwin Databus charge recovery: practical considerations. [Citation Graph (0, 0)][DBLP ] Conf ] You-Sung Chang , Bong-Il Park , Chong-Min Kyung Conforming inverted data store for low power memory. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrawan Soeleman , Kaushik Roy Ultra-low power digital subthreshold logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Suhwan Kim , Marios C. Papaefthymiou Single-phase source-coupled adiabatic logic. [Citation Graph (0, 0)][DBLP ] Conf ] Yumin Zhang , Xiaobo Hu , Danny Z. Chen Global register allocation for minimizing energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Subodh Gupta , Farid N. Najm Power macro-models for DSP blocks with application to high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] L. Richard Carley , Akshay Aggarwal A completey on-chip voltage regulation technique for low power digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Schwoerer , Dominique Morche , Patrice Senn Comparison of class A amplifiers for low-power and low-voltage switched capacitor applications. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Kruse , Eike Schmidt , Gerd Jochens , Wolfgang Nebel Lower and upper bounds on the switching activity in scheduled data flow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Subodh Gupta , Farid N. Najm Energy-per-cycle estimation at RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Luca Benini , Bruno Riccò , Giovanni De Micheli Efficient switching activity computation during high-level synthesis of control-dominated designs. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Marculescu , Diana Marculescu , Massoud Pedram Non-stationary effects in trace-driven power analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Sundararajan , Keshab K. Parhi Low power synthesis of dual threshold voltage CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jatuchai Pangjun , Sachin S. Sapatnekar Clock distribution using multiple voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Min Jiang , Tak K. Young , Kwang-Ting Cheng VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek De , Shekhar Borkar Technology and design challenges for low power and high performance. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeevan Amirtharajah , Thucydides Xanthopoulos , Anantha Chandrakasan Power scalable processing using distributed arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] David Garrett , Mircea R. Stan , Alvar Dean Challenges in clockgating for a low power ASIC methodology. [Citation Graph (0, 0)][DBLP ] Conf ] William E. Dougherty , Donald E. Thomas Modeling and automating selection of guarding techniques for datapath elements. [Citation Graph (0, 0)][DBLP ] Conf ] George Varghese , Hui Zhang , Jan M. Rabaey The design of a low energy FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Massoud Pedram Stochastic modeling of a power-managed system: construction and optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas L. Martin , Daniel P. Siewiorek The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Selective instruction compression for memory energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tajana Simunic , Luca Benini , Giovanni De Micheli Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ruchir Puri , Ching-Te Chuang Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Thierry Melly , Alain-Serge Porret , Christian C. Enz , M. Kayal , E. A. Vittoz A 1.2V, 430MHz, 4dBm power amplifier and a 250muW front-end, using a standard digital CMOS process. [Citation Graph (0, 0)][DBLP ] Conf ] Razieh Rofougaran , Tsung-Hsien Lin , William J. Kaiser CMOS front-end LNA-mixer of micropower RF wireless systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ayman ElSayed , Akbar Ali , Mohamed I. Elmasry Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel B. Schaevitz , Christopher Lin Passive precharge and rippled power logic (PPRPL). [Citation Graph (0, 0)][DBLP ] Conf ] Ali Keshavarzi , Siva Narendra , Shekhar Borkar , Charles F. Hawkins , Kaushik Roy , Vivek De Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Mondira Deb Pant , Pankaj Pant , D. Scott Wills , Vivek Tiwari An architectural solution for the inductive noise problem due to clock-gating. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Ramprasad , Ibrahim N. Hajj , Farid N. Najm An optimization technique for dual-output domino logic. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel , Sangyun Kim , Pei-Chuan Yeh , Kyeounsoo Kim Statistically optimized asynchronous barrel shifters for variable length codecs. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal C. H. Meier , Rob A. Rutenbar , L. Richard Carley Inverse polarity techniques for high-speed/low-power multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Lea Hwang Lee , Bill Moyer , John Arends Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Masselos , Koen Danckaert , Francky Catthoor , Constantinos E. Goutis , Hugo De Man A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Inoue , Tohru Ishihara , Kazuaki Murakami Way-predicting set-associative cache for high performance and low energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Chunho Lee , Johnson Kin , Miodrag Potkonjak , William H. Mangione-Smith Designing power efficient hypermedia processors. [Citation Graph (0, 0)][DBLP ] Conf ] HoonSang Jin , Myung-Soo Jang , Jin-Suk Song , Jin-Yong Lee , Taek-Soo Kim , Jeong-Taek Kong Dynamic power estimation using the probabilistic contribution measure (PCM). [Citation Graph (0, 0)][DBLP ] Conf ] Fari Assaderaghi Circuit styles and strategies for CMOS VLSI design on SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli System-level power optimization: techniques and tools. [Citation Graph (0, 0)][DBLP ] Conf ] 