Conferences in DBLP
Khalil Najafi Low-power micromachined microsystems (invited talk). [Citation Graph (0, 0)][DBLP ] Conf ] Thomas D. Burd , Robert W. Brodersen Design issues for dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Dragone , Akshay Aggarwal , L. Richard Carley An adaptive on-chip voltage regulation technique for low-power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrawan Soeleman , Kaushik Roy , Bipul Chandra Paul Robust ultra-low power sub-threshold DTMOS logic. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Sinha , Alice Wang , Anantha Chandrakasan Algorithmic transforms for efficient energy scalable computation. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli Operating-system directed power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Miodrag Potkonjak Energy minimization with guaranteed quality of service. [Citation Graph (0, 0)][DBLP ] Conf ] Tajana Simunic , Haris Vikalo , Peter W. Glynn , Giovanni De Micheli Energy efficient design of portable wireless systems. [Citation Graph (0, 0)][DBLP ] Conf ] P. Cusinato , F. Stefani , A. Baschirotto Power consumption reduction in high-speed Sigma-Delta bandpass modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Mattias Duppils , Christer Svensson Low power mixed analog-digital signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Pallotta , Francesco Centurelli , Alessandro Trifiletti A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Silvio Bolliri , Paolo Porcu , Luigi Raffo A micro-power mixed signal IC for battery-operated burglar alarm systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Massimo Poncino A recursive algorithm for low-power memory partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , Peter M. Kogge Optimization of high-performance superscalar architectures for energy efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor Pering , Thomas D. Burd , Robert W. Brodersen Voltage scheduling in the IpARM microprocessor system. [Citation Graph (0, 0)][DBLP ] Conf ] Jason M. Musicer , Jan M. Rabaey MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio G. M. Strollo , E. Napoli , Davide De Caro New clock-gating techniques for low-power flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Vinereanu , Sverre Lidholm An improved pass transistor synthesis method for low power, high speed CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Qu , Miodrag Potkonjak Achieving utility arbitrarily close to the optimal with limited energy. [Citation Graph (0, 0)][DBLP ] Conf ] Junghwan Choi , Jinhwan Jeon , Kiyoung Choi Power minimization of functional units partially guarded computation. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brockmeyer , Arnout Vandecappelle , Francky Catthoor Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Massoud Pedram Low power sequential circuit design by using priority encoding and clock gating. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni De Micheli , Tony Correale , Pietro Erratico , Srini Raghvendra , Hugo De Man , Jerry Frankil , Vivek Tiwari Do our low-power tools have enough horse power? (panel session) (title only). [Citation Graph (0, 0)][DBLP ] Conf ] Sven Mattisson Low-power considerations in the design of bluetooth (invited talk). [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed W. Allam , Mohab Anis , Mohamed I. Elmasry High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Ho Kwon , Joonho Lim , Soo-Ik Chae A three-port nRERL register file for ultra-low-energy applications. [Citation Graph (0, 0)][DBLP ] Conf ] Raguraman Venkatesan , Jeffrey A. Davis , Keith A. Bowman , James D. Meindl Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Athas Practical considerations of clock-powered logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendran Panda , David Blaauw , Rajat Chaudhry , Vladimir Zolotov , Brian Young , Ravi Ramaraju Model and analysis for combined package and on-chip power grid simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Naehyuck Chang , Kwanho Kim , Hyung Gyu Lee Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI. [Citation Graph (0, 0)][DBLP ] Conf ] Akshaye Sama , J. F. M. Theeuwen , M. Balakrishnan Speeding up power estimation of embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Kavel M. Büyüksahin , Farid N. Najm High-level power estimation with interconnect effects. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , Wei Hwang , S. C. Wilson , Ching-Te Chuang "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Dhar , Dragan Maksimovic Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Hee Won , Kiyoung Choi Low power self-timed Radix-2 division (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Lama H. Chandrasena , Michael J. Liebelt A rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Gerosa , Arianna Novo , Andrea Neviani Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Friedel Gerfers , Yiannos Manoli A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Chunlei Shi , Yue Wu , Mohammed Ismail Design of a low-power CMOS baseband circuit for wideband CDMA testbed (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Carl James Debono , Franco Maloberti , Joseph Micallef A low-voltage CMOS multiplier for RF applications (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Nose , Soo-Ik Chae , Takayasu Sakurai Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Masselos , S. Theoharis , Panagiotis Merakos , Thanos Stouraitis , Constantinos E. Goutis Low power synthesis of sum-of-products computation (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Acquaviva , Riccardo Scarsi A spatially-adaptive bus interface for low-switching communication (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Afzal Malik , Bill Moyer , Dan Cermak A low power unified cache architecture providing power and performance flexibility (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] G. Esakkimuthu , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin Memory system energy (poster session): influence of hardware-software optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Sathishkumar Udayanarayanan , Chaitali Chakrabarti Energy-efficient code generation for DSP56000 family (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Chung Cheng , Massoud Pedram Power-optimal encoding for DRAM address bus (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu Profile-driven code execution for low power dissipation (poster session). [Citation Graph (0, 0)][DBLP ] Conf ] Kyeounsoo Kim , Peter A. Beerel , Youpyo Hong An asynchronous matrix-vector multiplier for discrete cosine transform. [Citation Graph (0, 0)][DBLP ] Conf ] Khurram Muhammad , Robert B. Staszewski , Poras T. Balsara Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. [Citation Graph (0, 0)][DBLP ] Conf ] Vjekoslav Svilan , Masataka Matsui , James B. Burr Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Alain-Serge Porret , Thierry Melly , E. A. Vittoz , Christian C. Enz Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process. [Citation Graph (0, 0)][DBLP ] Conf ] F. Svelto , S. Deantoni , G. Montagna , R. Castello An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tirdad Sowlati , Sifen Luo Bias boosting technique for a 1.9GHz class AB RF amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Dai , Ramesh Harjani Analysis and design of low-phase-noise ring oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh R. Shanbhag , K. Soumyanath , Samuel Martin Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Ingrid Verbauwhede , Chris Nicol Low power DSP's for wireless communications (embedded tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] 