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Conferences in DBLP

International Symposium on Low Power Electronics and Design (islped)
2004 (conf/islped/2004)

  1. Ray Bryant
    Why hot chips are no longer "cool". [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:1- [Conf]
  2. Michael Liu, Wei-Shen Wang, Michael Orshansky
    Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:2-7 [Conf]
  3. Hari Ananthan, Chris H. Kim, Kaushik Roy
    Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:8-13 [Conf]
  4. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Technology exploration for adaptive power and frequency scaling in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:14-19 [Conf]
  5. Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz
    Experimental measurement of a novel power gating structure with intermediate power saving mode. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:20-25 [Conf]
  6. Hans M. Jacobson
    Improved clock-gating through transparent pipelining. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:26-31 [Conf]
  7. Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
    Microarchitectural techniques for power gating of execution units. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:32-37 [Conf]
  8. Amirali Baniasadi, Andreas Moshovos
    SEPAS: a highly accurate energy-efficient branch predictor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:38-43 [Conf]
  9. Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
    Understanding the energy efficiency of simultaneous multithreading. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:44-49 [Conf]
  10. Emil Talpes, Diana Marculescu
    Impact of technology scaling on energy aware execution cache-based microarchitectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:50-53 [Conf]
  11. Arindam Mallik, Matthew C. Wildrick, Gokhan Memik
    Design and implementation of correlating caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:58-61 [Conf]
  12. Nathaniel Pettis, Le Cai, Yung-Hsiang Lu
    Dynamic power management for streaming data. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:62-65 [Conf]
  13. Maged Ghoneima, Yehea I. Ismail
    Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:66-69 [Conf]
  14. Deming Chen, Jason Cong
    Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:70-73 [Conf]
  15. R. Reed Taylor, Herman Schmit
    Creating a power-aware structured ASIC. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:74-77 [Conf]
  16. Ravindra Jejurikar, Rajesh K. Gupta
    Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:78-81 [Conf]
  17. Hang Su, Peiliang Qiu, Qinru Qiu
    ESACW: an adaptive algorithm for transmission power reduction in wireless networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:82-85 [Conf]
  18. Shiva Shankar Ramani, Sanjukta Bhanja
    Any-time probabilistic switching model using bayesian networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:86-89 [Conf]
  19. Benton H. Calhoun, Anantha Chandrakasan
    Characterizing and modeling minimum energy operation for subthreshold circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:90-95 [Conf]
  20. Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
    Device optimization for ultra-low power digital sub-threshold operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:96-101 [Conf]
  21. Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
    Nanoscale CMOS circuit leakage power reduction by double-gate device. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:102-107 [Conf]
  22. Stefanos Kaxiras, Polychronis Xekalakis
    4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:108-113 [Conf]
  23. Chia-Lin Yang, Chien-Hao Lee
    HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:114-119 [Conf]
  24. Rui Min, Wen-Ben Jone, Yiming Hu
    Location cache: a low-power L2 cache system. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:120-125 [Conf]
  25. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:126-131 [Conf]
  26. Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft error and energy consumption interactions: a data cache perspective. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:132-137 [Conf]
  27. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Post-layout leakage power minimization based on distributed sleep transistor insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:138-143 [Conf]
  28. Vishal Khandelwal, Ankur Srivastava
    Active mode leakage reduction using fine-grained forward body biasing strategy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:150-155 [Conf]
  29. Songqing Zhang, Vineet Wason, Kaustav Banerjee
    A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:156-161 [Conf]
  30. Dexin Li, Pai H. Chou
    Maximizing efficiency of solar-powered systems by load matching. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:162-167 [Conf]
  31. Chulsung Park, Pai H. Chou
    Power utility maximization for multiple-supply systems by a load-matching switch. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:168-173 [Conf]
  32. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Dynamic voltage and frequency scaling based on workload decomposition. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:174-179 [Conf]
  33. Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
    Architecting voltage islands in core-based system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:180-185 [Conf]
  34. John Cornish
    Balanced energy optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:186- [Conf]
  35. Shreekant (Ticky) Thakkar
    Battery life challenges on future mobile notebook platforms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:187- [Conf]
  36. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
    Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:188-193 [Conf]
  37. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:194-199 [Conf]
  38. Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester
    A new algorithm for improved VDD assignment in low power dual VDD systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:200-205 [Conf]
  39. Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino
    Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:206-211 [Conf]
  40. Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
    Microarchitectural power modeling techniques for deep sub-micron microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:212-217 [Conf]
  41. Seongmoo Heo, Krste Asanovic
    Power-optimal pipelining in deep submicron technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:218-223 [Conf]
  42. Chandra Krintz, Ye Wen, Richard Wolski
    Application-level prediction of battery dissipation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:224-229 [Conf]
  43. Alireza Mehrnia, Babak Daneshrad
    Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:230-235 [Conf]
  44. Baohua Wang, Pinaki Mazumder
    On optimality of adiabatic switching in MOS energy-recovery circuit. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:236-239 [Conf]
  45. Joohee Kim, Marios C. Papaefthymiou
    Constant-load energy recovery memory for efficient high-speed operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:240-243 [Conf]
  46. Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay
    A comparative study of MOS VCOs for low voltage high performance operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:244-247 [Conf]
  47. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:248-251 [Conf]
  48. Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu
    A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:252-256 [Conf]
  49. Chuang Zhang, Dongsheng Ma, Ashok Srivastava
    Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:257-262 [Conf]
  50. Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
    Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:263-268 [Conf]
  51. Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti
    2.45 GHz power and data transmission for a low-power autonomous sensors platform. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:269-273 [Conf]
  52. Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty
    Managing standby and active mode leakage power in deep sub-micron design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:274-279 [Conf]
  53. Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene
    Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:280-285 [Conf]
  54. Mohamed Kawokgy, C. Andre T. Salama
    Low-power asynchronous viterbi decoder for wireless applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:286-289 [Conf]
  55. Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo
    A CMOS even harmonic mixer with current reuse for low power applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:290-295 [Conf]
  56. M. Ali-Bakhshian, K. Sadeghi
    A novel continuous-time common-mode feedback for low-voltage switched-OPAMP. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:296-300 [Conf]
  57. Yijun Liu, Stephen B. Furber
    The design of a low power asynchronous multiplier. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:301-306 [Conf]
  58. Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang
    Low-power fixed-width array multipliers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:307-312 [Conf]
  59. Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
    Low-power carry-select adder using adaptive supply voltage based on input vector patterns. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:313-318 [Conf]
  60. Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Reducing pipeline energy demands with local DVS and dynamic retiming. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:319-324 [Conf]
  61. Supriyo Datta
    Understanding nanoscale conductors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:325- [Conf]
  62. Kim M. Hazelwood, David Brooks
    Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:326-331 [Conf]
  63. Baohua Wang, Pinaki Mazumder
    On optimality of adiabatic switching in MOS energy-recovery circuit. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:332-337 [Conf]
  64. Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jin-Soo Kim
    Energy-aware demand paging on NAND flash-based embedded storages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:338-343 [Conf]
  65. Diana Marculescu
    Application adaptive energy efficient clustered architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:344-349 [Conf]
  66. Sani R. Nassif
    The impact of variability on power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:350- [Conf]
  67. Bo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede
    Reducing radio energy consumption of key management protocols for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:351-356 [Conf]
  68. Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
    Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:357-362 [Conf]
  69. Vijay Raghunathan, Trevor Pering, Roy Want, Alex Nguyen, Peter Jensen
    Experience with a low power wireless mobile computing platform. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:363-368 [Conf]
  70. Luca Negri, Mariagiovanna Sami, David Macii, Alessandra Terranegra
    FSM--based power modeling of wireless protocols: the case of bluetooth. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:369-374 [Conf]
  71. Mohamed Elgebaly, Manoj Sachdev
    Efficient adaptive voltage scaling system through on-chip critical path emulation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:375-380 [Conf]
  72. Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
    An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:381-386 [Conf]
  73. Youngjin Cho, Naehyuck Chang
    Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:387-392 [Conf]
  74. Woonseok Kim, Jihong Kim, Sang Lyul Min
    Preemption-aware dynamic voltage scaling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:393-398 [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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