Conferences in DBLP
Cristoph Kutter Design challenges for mobile communication devices. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Raychowdhury , Xuanyao Fong , Qikai Chen , Kaushik Roy Analysis of super cut-off transistors for ultralow power digital logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joyce Kwong , Anantha P. Chandrakasan Variation-driven device sizing for minimum energy sub-threshold circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ik Joon Chang , Jae-Joon Kim , Kaushik Roy Robust level converter design for sub-threshold logic. [Citation Graph (0, 0)][DBLP ] Conf ] Nathaniel Guilar , Albert Chen , Travis Kleeburg , Rajeevan Amirtharajah Integrated solar energy harvesting and storage. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Rodríguez , Bruce Jacob Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). [Citation Graph (0, 0)][DBLP ] Conf ] Eric L. Hill , Mikko H. Lipasti Stall cycle redistribution in a transparent fetch pipeline. [Citation Graph (0, 0)][DBLP ] Conf ] Deniz Balkan , Joseph J. Sharkey , Dmitry Ponomarev , Kanad Ghose Selective writeback: exploiting transient values for energy-efficiency and performance. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Sasaki , Masaaki Kondo , Hiroshi Nakamura Energy-efficient dynamic instruction scheduling logic through instruction grouping. [Citation Graph (0, 0)][DBLP ] Conf ] Grigorios Magklis , Pedro Chaparro , José González , Antonio González Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] YongKang Zhu , David H. Albonesi Synergistic temperature and energy management in GALS processor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hidehiro Fujiwara , Koji Nii , Junichi Miyakoshi , Yuichiro Murachi , Yasuhiro Morita , Hiroshi Kawaguchi , Masahiko Yoshimoto A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. [Citation Graph (0, 0)][DBLP ] Conf ] Jonggab Kil , Jie Gu , Chris H. Kim A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. [Citation Graph (0, 0)][DBLP ] Conf ] Harmander Deogun , Robert M. Senger , Dennis Sylvester , Richard B. Brown , Kevin J. Nowka A dual-VDD boosted pulsed bus technique for low power and low leakage operation. [Citation Graph (0, 0)][DBLP ] Conf ] Keith A. Bowman , James Tschanz , Muhammad M. Khellah , Maged Ghoneima , Yehea I. Ismail , Vivek De Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Pong-Fei Lu , Nianzheng Cao , Leon J. Sigal , Pieter Woltgens , R. Robertazzi , David Heidel A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Chung Cheng , Chih-Fu Hsu , Chain-Fu Chao Temporal vision-guided energy minimization for portable displays. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Rizo-Morente , Miguel Casas-Sanchez , Chris J. Bleakley Dynamic current modeling at the instruction level. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunseok Lee , Trevor N. Mudge , Chaitali Chakrabarti Reducing idle mode power in software defined radio terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Maria G. Koziri , Georgios I. Stamoulis , Ioannis Katsavounidis Power reduction in an H.264 encoder through algorithmic and logic transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Varatkar , Naresh R. Shanbhag Energy-efficient motion estimation using error-tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Javid Jaffari , Mohab Anis Variability-aware device optimization under ION and leakage current constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT [Citation Graph (0, 0)][DBLP ] Conf ] Tae-Hyoung Kim , Hanyong Eom , John Keane , Chris H. Kim Utilizing reverse short channel effect for optimal subthreshold circuit design. [Citation Graph (0, 0)][DBLP ] Conf ] Jabulani Nyathi , Brent Bero Logic circuits operating in subthreshold voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Jianwei Zhang , Yizheng Ye , Binda Liu A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Wang , Lei Wang Thread-associative memory for multicore and multithreaded computing. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Hsiang Lin , Chia-Lin Yang , Ku-Jei King Hierarchical value cache encoding for off-chip data bus. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Jin , Sangyeun Cho Reducing cache traffic and energy with macro data load. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Reimer , Arne Schulz , Wolfgang Nebel Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Yiyu Shi , Lei He , Tanay Karnik Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. [Citation Graph (0, 0)][DBLP ] Conf ] Ashutosh Chakraborty , K. Duraisami , Ashoka Visweswara Sathanur , Prassanna Sithambaram , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Lin , Yu Hu , Lei He , Vijay Raghunat An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] V. Mahalingam , N. Ranganathan , Justin E. Harlow III A novel approach for variation aware power minimization during gate sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Hsu , Sadaf Zahedi , Aman Kansal , Mani B. Srivastava , Vijay Raghunathan Adaptive duty cycling for energy harvesting systems. [Citation Graph (0, 0)][DBLP ] Conf ] Le Cai , Yung-Hsiang Lu Power reduction of multiple disks using dynamic cache resizing and speed control. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Daniel Burns , Douglas Holzhauer Lifetime aware resource management for sensor network using distributed genetic algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Farhan Simjee , Pai H. Chou Everlast: long-life, supercapacitor-operated wireless sensor node. [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif Model to hardware matching: for nano-meter scale technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Majid Sarrafzadeh , Foad Dabiri , Roozbeh Jafari , Tammara Massey , Ani Nahapetian Low power light-weight embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Barry Dennington Low power design from technology challenge to great products. [Citation Graph (0, 0)][DBLP ] Conf ] Baozhen Yu , Michael L. Bushnell A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Domenik Helms , Günter Ehmen , Wolfgang Nebel Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. [Citation Graph (0, 0)][DBLP ] Conf ] W. T. Cheung , N. Wong Power optimization in a repeater-inserted interconnect via geometric programming. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Hu , Vishwani D. Agrawal Input-specific dynamic power optimization for VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Wang , Yongpan Liu , Rong Luo , Huazhong Yang , Hui Wang Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Zeng , Kanad Ghose Register file caching for energy efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Elham Safi , Andreas Moshovos , Andreas G. Veneris L-CBF: a low-power, fast counting bloom filter architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Sharifkhani , Manoj Sachdev A low power SRAM architecture based on segmented virtual grounding. [Citation Graph (0, 0)][DBLP ] Conf ] Ke Meng , Russ Joseph Process variation aware cache leakage management. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Garg , Fernando Castro , Michael C. Huang , Daniel Chaver , Luis Piñuel , Manuel Prieto Substituting associative load queue with simple hash tables in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Amin Shameli , Payam Heydari A novel power optimization technique for ultra-low power RFICs. [Citation Graph (0, 0)][DBLP ] Conf ] Alessio Facen , Andrea Boni A CMOS analog frontend for a passive UHF RFID tag. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Henzler , Siegmar Koeppe High-speed low-power frequency divider with intrinsic phase rotator. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Chaitali Chakrabarti , Naehyuck Chang An optimal analytical solution for processor speed control with thermal constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Vidyasagar Nookala , David J. Lilja , Sachin S. Sapatnekar Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. [Citation Graph (0, 0)][DBLP ] Conf ] James Donald , Margaret Martonosi Power efficiency for variation-tolerant multicore processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yoonjin Kim , Ilhyun Park , Kiyoung Choi , Yunheung Paek Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Wonbok Lee , Kimish Patel , Massoud Pedram Dynamic thermal management for MPEG-2 decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Song Guo , Hoi Lee A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Changbo Long , Sasank Reddy , Sudhakar Pamarti , Lei He , Tanay Karnik Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. [Citation Graph (0, 0)][DBLP ] Conf ] Anas A. Hamoui , T. Alhajj , Mohammad Taherzadeh-Sani Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Amelifard , Farzan Fallah , Massoud Pedram Low-power fanout optimization using MTCMOS and multi-Vt techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hanson , Dennis Sylvester , David Blaauw A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Saumya Chandra , Kanishka Lahiri , Anand Raghunathan , Sujit Dey Considering process variations during system-level power analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mirko Loghi , Massimo Poncino , Luca Benini Synchronization-driven dynamic speed scaling for MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] W. L. Bircher , L. K. John Power phase variation in a commercial server workload. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Seung Woo Son Reducing power through compiler-directed barrier synchronization elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Hakduran Koc , Ozcan Ozturk , Mahmut T. Kandemir , Sri Hari Krishna Narayanan , Ehat Ercanli Minimizing energy consumption of banked memories using data recomputation. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hanson , Bo Zhai , David Blaauw , Dennis Sylvester , Andres Bryant , Xinlin Wang Energy optimality and variability in subthreshold design. [Citation Graph (0, 0)][DBLP ] Conf ] Benton H. Calhoun , Alice Wang , Naveen Verma , Anantha Chandrakasan Sub-threshold design: the challenges of minimizing circuit energy. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Raghunathan , Pai H. Chou Design and power management of energy harvesting embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wintermayr , Reiner W. Hartenstein , Heinrich Meyr , Steve Leibson Flexibility and low power: a contradiction in terms? [Citation Graph (0, 0)][DBLP ] Conf ] Malav Shah Efficient scan-based BIST scheme for low power testing of VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Gu , John Keane , Chris H. Kim Modeling and analysis of leakage induced damping effect in low voltage LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Wei Huang , Hsin-Hsin Ho , Ke-Horng Chen , Sy-Yen Kuo Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC converters. [Citation Graph (0, 0)][DBLP ] Conf ] Dongsheng Ma , Janet Meiling Wang , Pablo Vazquas Adaptive on-chip power supply with robust one-cycle control technique. [Citation Graph (0, 0)][DBLP ] Conf ] Dongsheng Ma Robust multiple-phase switched-capacitor DC-DC converter with digital interleaving regulation scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Jin , Chi-Ying Tsui A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Chen , Song Jiang , Xiaodong Zhang SmartSaver: turning flash drive into a disk energy saver for mobile computers. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Wei Tseng , Han-Lin Li , Chia-Lin Yang An energy-efficient virtual memory system with flash memory as the secondary storage. [Citation Graph (0, 0)][DBLP ] Conf ] Jianli Zhuo , Chaitali Chakrabarti , Naehyuck Chang , Sarma B. K. Vrudhula Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. [Citation Graph (0, 0)][DBLP ] Conf ] 