Conferences in DBLP
Message from the Co-Chairs. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Symposium Chair. [Citation Graph (0, 0)][DBLP ] Conf ] Reviewers. [Citation Graph (0, 0)][DBLP ] Conf ] Dan W. Hammerstrom Computational Neurobiology Meets Semiconductor Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Shen , Motoi Inaba , Koichi Tanno , Okihiko Ishizuka Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Matsumoto , Yoshinori Ueda , Isami Nomoto The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Syuto , Jing Shen , Koichi Tanno , Okihiko Ishizuka Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Alioune Ngom , Ivan Stojmenovic , Ratko Tosic The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Mitchell A. Thornton , David Wessels MDD-Based Synthesis of Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Susanto Rahardja Fast Transforms for Multiple-Valued Input Binary Output PLI Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Mitchell A. Thornton Computation of Spectral Information from Logic Netlists. [Citation Graph (0, 0)][DBLP ] Conf ] Jong O. Kim , Parag K. Lala , Young Gun Kim , Heung-Soo Kim Fault Analysis of the Multiple Valued Logic Using Spectral Method. [Citation Graph (0, 0)][DBLP ] Conf ] Jacek M. Zurada Neural Networks: Binary Monotonic and Multiple-Valued. [Citation Graph (0, 0)][DBLP ] Conf ] Szymon Jaroszewicz , Dan A. Simovici Data Mining of Weak Functional Decompositions. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Chojnacki , Lech Józwiak Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Kyoichi Nakashima Some Properties of Discrete Interval Truth Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoko Ninomiya , Masao Mukaidono Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Agata Ciabattoni On Urquhart's C Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Martine De Cock , Etienne E. Kerre A New Class of Fuzzy Modifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Karsten Strehl , Claudio Moraga , Karl-Heinz Temme , Radomir S. Stankovic Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases. [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Thiele On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Svetlana N. Yanushkevich , Jon T. Butler , Gerhard W. Dueck , Vlad P. Shmerko Experiments on FPRM Expressions for Partially Symmetric Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Tsutomu Sasao Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Susanto Rahardja , Bogdan J. Falkowski A New Algorithm to Compute Quaternary Reed-Muller Expansions. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Stoica Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz A. Brzozowski De Morgan Bisemilattices. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Aguzzoli , Brunella Gerla Finite-Valued Approximations of Product Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Yann Loyer , Nicolas Spyratos , Daniel Stamate Integration of Information in Four-Valued Logics under Non-Uniform Assumptions. [Citation Graph (0, 0)][DBLP ] Conf ] Dragan Jankovic , Wolfgang Günther , Rolf Drechsler Lower Bound Sifting for MDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Iguchi , Tsutomu Sasao , Munehiro Matsuura Implementation of Multiple-Output Functions Using PQMDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Milena Stankovic , Jaakko Astola , Karen Egiazarian Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , Abdullah Al-Mutawa Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeon Kyeong Seong , Jai Seok Choi , Boo Sik Shin , Heung-Soo Kim Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Xuanchang Zhou Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Sack , Elena Dubrova , Christoph Meinel Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Schmiedle , Wolfgang Günther , Rolf Drechsler Dynamic Re-Encoding During MDD Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Nobuyuki Matsui Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tadeusz Luba , Claudio Moraga , Svetlana N. Yanushkevich , M. Opoka , Vlad P. Shmerko Evolutionary Multi-Level Network Synthesis in Given Design Style. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hozumi , Osamu Kakusho , Kazuharu Yamato An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Svetlana N. Yanushkevich , Denis V. Popel , Vlad P. Shmerko , V. Cheushev , Radomir S. Stankovic Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Syoji Kobashi , Naotake Kamiura , Yuri T. Kitamura , Toshio Yanagida On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Lip-San Lim Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra. [Citation Graph (0, 0)][DBLP ] Conf ] David Rine , Raiek Alnakari A Four-Valued Logic B(4) of E(9) for Modeling Human Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo Düntsch , Wendy MacCaull , Ewa Orlowska Structures with Many-Valued Information and Their Relational Proof Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Uemura , Toshio Baba Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Noung Byun , Chol-U Lee , Seung-Yong Park , Heung-Soo Kim A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Waho , Kazufumi Hattori , Kouji Honda Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro F. González , Mayukh Bhattacharya , Shriram Kulkarni , Pinaki Mazumder Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Beckert , Reiner Hähnle , Felip Manyà The 2-SAT Problem of Regular Signed CNF Formulas. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Ganzinger , Viorica Sofronie-Stokkermans Chaining Techniques for Automated Theorem Proving in Many-Valued Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Takafumi Aoki , Kimihiko Nakazawa , Tatsuo Higuchi High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Jabri , Ki-Young Park , Soo-Young Lee , Terrence J. Sejnowski Properties of Independent Components of Self-Motion Optical Flow. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bauer , R. Alexis , Greg Atwood , B. Baltar , Al Fazio , K. Frary , M. Hensel , M. Ishac , J. Javanifard , M. Landgraf , D. Leak , K. Loe , Duane Mills , P. Ruby , R. Rozman , S. Sweha , S. Talreja , K. Wojciechowski A Multilevel-Cell 32MB Flash Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Olson , K. Wayne Current Hardware Implementation of ``Supplementary Symmetrical Logic Circuit Structure'' Concepts. [Citation Graph (0, 0)][DBLP ] Conf ] K. Wayne Current Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Tsukasa Ike , Michitaka Kameyama Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Miyakawa , Ivo G. Rosenberg Rigidity Problem of Autodual Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Lucien Haddad , Hajime Machida , Ivo G. Rosenberg On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Nagata , D. Michael Miller , Masao Mukaidono Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuo Takahashi , Akira Fujiwara , Yukinori Ono , Katsumi Murase Silicon Single-Electron Devices and Their Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Hiromitsu Kimura , Michitaka Kameyama DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Yuminaka , Osamu Katoh , Yoshisat Sasaki , Takafumi Aoki , Tatsuo Higuchi An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. [Citation Graph (0, 0)][DBLP ] Conf ] Shunichi Kaeriyama , Takahiro Hanyu , Michitaka Kameyama Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Mitchell A. Thornton , Rolf Drechsler , Wolfgang Günther A Method for Approximate Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Massoud Pedram Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova , Harald Sack Probabilistic Verification of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] 