Conferences in DBLP
Jonathan Rose Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Yuki Tsuji , Takao Waho Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Raychowdhury , Kaushik Roy A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomohiro Takahashi , Takahiro Hanyu Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Haque Mohammad Munirul , Michitaka Kameyama Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Viorica Sofronie-Stokkermans Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Aguzzoli Uniform Description of Calculi for All t-Norm Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Mayuka F. Kawaguchi , Masaaki Miyakoshi Weakly Associative Functions on [0, 1] as Logical Connectives. [Citation Graph (0, 0)][DBLP ] Conf ] Brunella Gerla Automata over MV-Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Gilles Brassard Quantum Communication Complexity: A Survey. [Citation Graph (0, 0)][DBLP ] Conf ] Mozammel H. A. Khan , Marek A. Perkowski , Mujibur R. Khan Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kerntopf , Marek A. Perkowski , Mozammel H. A. Khan On Universality of General Reversible Multiple-Valued Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] D. Michael Miller , Gerhard W. Dueck , Dmitri Maslov A Synthesis Method for MVL Reversible Logi. [Citation Graph (0, 0)][DBLP ] Conf ] Anas N. Al-Rabadi Reversible Fast Permutation Transforms for Quantum Circuit Synthesi. [Citation Graph (0, 0)][DBLP ] Conf ] Anas Al-Rabadi Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Lucien Haddad , Dietlinde Lau On Partial Clones containing Maximal Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Hajime Machida , Ivo G. Rosenberg Monoids whose Centralizer is the Least Clone. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Pogosyan , Ivo G. Rosenberg Algebraic Properties of Totally Irreducible Elements of Clone Lattices. [Citation Graph (0, 0)][DBLP ] Conf ] Jovanka Pantovic , Gradimir Vojvodic Minimal Partial Hyperclones on a Two-Element Set. [Citation Graph (0, 0)][DBLP ] Conf ] B. A. Romov Some Properties of Local Partial Clones on an Infinite Set. [Citation Graph (0, 0)][DBLP ] Conf ] Hideki Fukuda Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Omid Mirmotahari , Yngvar Berg A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Mihai Optimizing the Defuzzifier Timing for the Fuzzy Control of a Servodrive. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Moraga A Metasemantics to Refine Fuzzy If-Then Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Alioune Ngom , Dan A. Simovici , Ivan Stojmenovic Evolutionary Strategy for Learning Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Cicilia C. Lozano , Susanto Rahardja Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5). [Citation Graph (0, 0)][DBLP ] Conf ] K. J. Adams , J. McGregor On the Optimisation of Reed-Muller Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Cicilia C. Lozano , Susanto Rahardja Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5). [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Claudio Moraga , Jaakko Astola Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Mochizuki , Takashi Takeuchi , Takahiro Hanyu Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Soo Jin Park , Byoung Hee Yoon , Kwang Sub Yoon , Heung Soo Kim Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel H. Y. Teng , Ronald J. Bolton A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Omid Mirmotahari , Yngvar Berg A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Shinobu Nagayama , Tsutomu Sasao On the Minimization of Average Path Lengths for Heterogeneous MDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Dragan Jankovic , Radomir S. Stankovic , Rolf Drechsler Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Jaakko Astola Edge-Valued Decision Diagrams for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Görschwin Fey , Rolf Drechsler , Maciej J. Ciesielski Algorithms for Taylor Expansion Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Dietmar Schweigert Polynomial Functions on a Central Relation. [Citation Graph (0, 0)][DBLP ] Conf ] Sergiu Rudeanu , Dan A. Simovici A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Ansótegui , Ramón Béjar , Alba Cabiscol , Felip Manyà The Interface between P and NP in Signed CNF Formulas. [Citation Graph (0, 0)][DBLP ] Conf ] Michiro Kondo Characterization Theorem of Lattice Implication Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuhiko Degawa , Takafumi Aoki , Tatsuo Higuchi , Hiroshi Inokawa , Yasuo Takahashi A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Inokawa , Yasuo Takahashi , Katsuhiko Degawa , Takafumi Aoki , Tatsuo Higuchi A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Svetlana N. Yanushkevich , Vlad P. Shmerko , L. Guy , D. C. Lu Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Arnon Avron , Iddo Lev Non-Deterministic Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Denis V. Popel , Elena I. Popel Controlling Uncertainty in Discretization of Continuous Data. [Citation Graph (0, 0)][DBLP ] Conf ] Charles G. Morgan Many Valued Probability Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Yukihiro Iguchi , Tsutomu Sasao , Munehiro Matsuura A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , Louai Al-Awami Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS Realization. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Moinul Islam Zaber , Md. Rafiqul Islam , Md. Mazder Rahman On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Haque Mohammad Munirul , Michitaka Kameyama Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Ishida , Naofumi Homma , Takafumi Aoki , Tatsuo Higuchi Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. [Citation Graph (0, 0)][DBLP ] Conf ] Hiromitsu Kimura , Kostas Pagiamtzis , Ali Sheikholeslami , Takahiro Hanyu A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Yngvar Berg , Snorre Aunet , Øivind Næss , Omid Mirmotahari Basic Multiple-Valued Functions Using Recharge CMOS Logic. [Citation Graph (0, 0)][DBLP ] Conf ] 