Conferences in DBLP
Shinya Hasuo High-Speed Digital Circuits for a Josephson Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Mititada Morisue , Fu-Qiang Li A Superconducting Ternary Systolic Array Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Lutz J. Micheel Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Sen Jung Wei , Hung Chang Lin Unique Folding and Hysteresis Characteristics of RTD for Multi-Valued Logic and Counting Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Fujio Miyawaki , Kazuharu Yamato Easily Testable Multiple-Valued Cellular Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Geetani Edirisooriya , John P. Robinson Aliasing in Multiple-Valued Test Data Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Hassan M. Razavi , Paul W. Wong A New Balanced Gate for Structural Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard W. Dueck Direct Cover MVL Minimization with Cost-Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard W. Dueck , Robert C. Earle , Parthasarathy P. Tirumalai , Jon T. Butler Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Chyan Yang , Onur Oral Experiences of Parallel Processing with Direct Cover Algorithms for Multiple-Valued Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Lun J. Hu Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous Two-Layered Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Tatsuki Watanabe , Masayuki Matsumoto Layered MVL Neural Networks Capable of Recognizing Translated Characters. [Citation Graph (0, 0)][DBLP ] Conf ] Joo-Hwee Lim , Ho-Chung Lui , Hoon heng Teh A Deductive Neural-Logic System. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad Lei , Zvonko G. Vranesic Towards the Realization of 4-Valued CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , H. Choy Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Haga An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the p-Valued Logical Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyomichi Araki , Masayuki Takada , Masakatu Morii On the Efficient Decoding of Reed-Solomon Codes Based on GMD Criterion. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Doherty , Witold Lukaszewicz Defaults as First-Class Citizens. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Etiemble On the Performance of Multivalued Integrated Circuits: Past, Present and Future. [Citation Graph (0, 0)][DBLP ] Conf ] David Wessels , Jon C. Muzio Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masayoshi Sakai , Masakazu Kato , Koichi Futsuhara , Masao Mukaidono Application of Fail-Safe Multiple-Valued Logic to Control of Power Press. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Min Wang , Chung-Len Lee , Jwu E. Chen Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. C. Canals Frau , Aldo V. Figallo (n+1)-Valued Modal Implicative Semilattices. [Citation Graph (0, 0)][DBLP ] Conf ] Jizhong Shen Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I). [Citation Graph (0, 0)][DBLP ] Conf ] Edward K. F. Lee , P. Glenn Gulak Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Kazutaka Taniguchi , Mamoru Sasaki , Yutaka Ogata , Fumio Ueno , Takahiro Inoue Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply Voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , M. I. Mahroos On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] K. Wayne Current A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoichi Nakashima , Noboru Takagi On Multiple-Valued Logic Functions Monotonic with Respect to Ambiguity. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Kyoichi Nakashima , Masao Mukaidono Fundamental Properties of Extended Kleene-Stone Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Ratko Tosic , Ivan Stojmenovic , Dan A. Simovici , Corina Reischer On Set-Valued Functions and Boolean Collections. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Pöschel , M. Reichel Rectangular Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Marek A. Perkowski A Universal Logic Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Kouichi Takeda , Tatsuo Higuchi Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Maeda , Takafumi Aoki , Tatsuo Higuchi Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Wayne Mills Area-Efficient Implication Circuits for Very Dense Lukasiewicz Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Miyakawa , Akihiro Nozaki , Grant Pogosyan , Ivo G. Rosenberg Semigrid Sets of Central Relations Over a Finite Domain. [Citation Graph (0, 0)][DBLP ] Conf ] V. Lashkia Amplification of the Functional Closure Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Agnes Szendrei A Completeness Criterion for Semi-Affine Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuhiko Shimabukuro , Michitaka Kameyama , Tatsuo Higuchi Design of a Multiple-Valued VLSI Processor for Digital Control. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Honda , Michitaka Kameyama , Tatsuo Higuchi Residue Arithmetic Based Multiple-Valued VLSI Image Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Kawahito , Y. Mitsui , Makoto Ishida , Tetsuro Nakamura Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Philipp W. Besslich , E. A. Trachtenberg Binary Input/Ternary Output Switching Circuits Designed Via the Sign Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] R. Tomczuk , D. Michael Miller Autocorrelation Techniques for Multi-Bit Decoder PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic Some Remarks on Fourier Transform and Differential Operators for Digital Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Susan W. Butler , Jon T. Butler Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. [Citation Graph (0, 0)][DBLP ] Conf ] Saneaki Tamaki , Michitaka Kameyama , Tatsuo Higuchi Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Fujio Miyawaki , Kazuharu Yamato Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Mou Hu , Shensheng Xu , Kenneth C. Smith On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary MOS Bridge Circuits and Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Benchu Fei , Nan Zhuang Fast Logic Synthesis Based Upon Ternary Universal Logic Module f [Citation Graph (0, 0)][DBLP ] Conf ] Fumio Ueno , Takahiro Inoue , Badur-ul-Haque Baloch , Takayoshi Yamamoto An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy Inference. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinori Yamamoto A Meaningful Infinite-Valued Switching Function - Fuzzy Threshold Function and Its Application to Process Control. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Shirai , Fumio Ueno , Takahiro Inoue , Motohiro Inoue , Kouji Tasaki Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode Fuzzy State Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Ito , Takashi Matsubara , Takakazu Kurokawa , Yoshiaki Koga A Proposal of Fault-Checking Fuzzy Control. [Citation Graph (0, 0)][DBLP ] Conf ] Berthold Harking , Claudio Moraga Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marek A. Perkowski The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Nakamura On a Logic Based on Fuzzy Modalities. [Citation Graph (0, 0)][DBLP ] Conf ] Zuliang Shen , Liya Ding , Ho-Chung Lui , Pei-Zhuang Wang , Masao Mukaidono Revision Principle for Approximate Reasoning-Based on Semantic Revising Method. [Citation Graph (0, 0)][DBLP ] Conf ] Heinz J. Skala On Yager's Aggregation Operators. [Citation Graph (0, 0)][DBLP ] Conf ] Lotfi A. Zadeh Fuzzy Logic and the Calculus of Fuzzy If-Then Rules. [Citation Graph (0, 0)][DBLP ] Conf ] 