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Conferences in DBLP
Message from the Symposium Chairs. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:- [Conf]
Organizing Committee. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:- [Conf]
Message from the Program Chair. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:- [Conf]
List of Reviewers. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:- [Conf]
Two New Awards. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:- [Conf]
- Barry C. Sanders
Classical vs Quantum Fingerprinting. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:2-5 [Conf]
- Ivo G. Rosenberg, Dan A. Simovici
An Abstract Axiomatization of the Notion of Entropy. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:8-13 [Conf]
- Seiki Akama, Yasunori Nagata
On Prior's Three-Valued Modal Logic Q. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:14-19 [Conf]
- Walter Alexandre Carnielli
Polynomial Ring Calculus for Many-Valued Logics. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:20-25 [Conf]
- Michiro Kondo, Mayuka F. Kawaguchi
Partially Ordered Set with Residuated t-norm. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:26-29 [Conf]
- Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:32-38 [Conf]
- Marina Alexandra Lyshevski
Multi-Valued DNA-Based Electronic Nanodevices. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:39-42 [Conf]
- Keisuke Eguchi, Masaru Chibashi, Takao Waho
A Design of 10-GHz Delta-Sigma Modulator using a 4-Level Differential Resonant-Tunneling Quantizer. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:43-47 [Conf]
- Sergey Edward Lyshevski
Multi-Valued Nanoelectronics With Fullerenes. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:48-53 [Conf]
- Henning Gundersen, Renè Jensen, Yngvar Berg
A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:54-58 [Conf]
- Marek A. Perkowski, Jacob Biamonte, Martin Lukac
Test Generation and Fault Localization for Quantum Circuits. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:62-68 [Conf]
- Bernd Steinbach, Christian Lang
Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX Gates. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:69-74 [Conf]
- Yukihiro Iguchi, Tsutomu Sasao
Hardware to Compute Walsh Coefficients. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:75-81 [Conf]
- Sergey Edward Lyshevski
Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:82-87 [Conf]
- Nabil Abu-Khader, Pepe Siy
Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:88-93 [Conf]
- Jovanka Pantovic, Gradimir Vojvodic
On the Partial Hyperclone Lattice. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:96-100 [Conf]
- Lucien Haddad, Ivo G. Rosenberg
Partial Clones Determined by Concatenated Relations. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:101-106 [Conf]
- Masahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi
Semirigid Equivalence Relations - A New Proof Method. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:107-112 [Conf]
- Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:114-119 [Conf]
- Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:120-125 [Conf]
- Emre Özer, Resit Sendag, David Gregg
Multiple-Valued Caches for Power-Efficient Embedded Systems. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:126-131 [Conf]
- Chris Winstead
Analog Soft Decoding for Multi-Level Memories. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:132-137 [Conf]
- Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:138-143 [Conf]
- Hideki Fukuda
Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:144-151 [Conf]
- Phil Serchuk
The Alleged Limitations of Fuzzy Control. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:154-159 [Conf]
- Claudio Moraga, Rodrigo Salas
A New Aspect for the Optimization of Fuzzy If-Then Rules. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:160-165 [Conf]
- Michael P. Frank
Approaching the Physical Limits of Computing. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:168-185 [Conf]
- Radomir S. Stankovic, Claudio Moraga, Jaakko Astola
Remarks on the Structure of Matrix-Valued Spectral Transforms on Finite Non-Abelian Groups. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:188-193 [Conf]
- Mitchell A. Thornton
The Karhunen-Loève Transform of Discrete MVL Functions. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:194-199 [Conf]
- Cheng Fu, Bogdan J. Falkowski
Properties and Relations of Quaternary Linearly Independent Helix Transformations. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:200-205 [Conf]
- Bogdan J. Falkowski, Cheng Fu
Classes of Fastest Quaternary Linearly Independent Transformations. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:206-211 [Conf]
- Zoran Majkic
Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based Logic. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:214-220 [Conf]
- Michel Serfati
A Note on Triangulation of PostAlgebras and "Leibnizian" Lattices. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:221-226 [Conf]
- Hajime Machida, Ivo G. Rosenberg
Centralizers of Monoids Containing the Symmetric Group. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:227-233 [Conf]
- Marek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:236-248 [Conf]
- Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Controlling the Memory During Manipulation of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:250-255 [Conf]
- Tsutomu Sasao
Radix Converters: Complexity and Implementation by LUT Cascades. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:256-263 [Conf]
- Elena N. Zaitseva, Vitaly G. Levashenko, K. Matiasko, Seppo Puuronen
Dynamic Reliability Indices for k-out-of-n Multi-State System. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:264-269 [Conf]
- Jacqueline E. Rice, Jon C. Muzio
A Characterization of Antisymmetry in Boolean and Multi-Valued Functions. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:270-275 [Conf]
- Daniel H. Y. Teng, Ronald J. Bolton
Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:276-281 [Conf]
- Stefano Aguzzoli, Brunella Gerla
Normal Forms for the One-Variable Fragment of Hájek's Basic Logic. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:284-289 [Conf]
- Carlos Ansótegui, Felip Manyà
Mapping Many-Valued CNF Formulas to Boolean CNF Formulas. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:290-295 [Conf]
- Arnon Avron, Anna Zamansky
Quantification in Non-Deterministic Multi-Valued Structures. [Citation Graph (0, 0)][DBLP]
ISMVL, 2005, pp:296-301 [Conf]
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