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Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
1993 (conf/ismvl/1993)

  1. D. Michael Miller
    Multiple-Valued Logic Design Tools. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:2-11 [Conf]
  2. Qinhua Hong, Benchu Fei, Haomin Wu, Marek A. Perkowski, Nan Zhuang
    Fast Synthesis for Ternary Reed-Muller Expansion. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:14-16 [Conf]
  3. Cem Yildirim, Jon T. Butler, Chyan Yang
    Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:17-23 [Conf]
  4. Antonio Lloris-Ruíz, Juan Francisco Gómez-Lopera, Ramón Román-Roldán
    Entropic Minimization of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:24-28 [Conf]
  5. Yutaka Hata, Takahiro Hozumi, Kazuharu Yamato
    Gate Model Networks for Minimization of Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:29-34 [Conf]
  6. Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono
    A Canonical Disjunctive Form of Extended Kleene-Stone Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:36-41 [Conf]
  7. Zuoquan Lin
    Three-Valued Nonmonotonic Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:42-47 [Conf]
  8. James J. Lu, Neil V. Murray, Erik Rosenthal
    Signed Formulas and Annotated Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:48-53 [Conf]
  9. E. R. Harley, Zbigniew Stachniak
    Minimal Resolution Proof Systems for Finitely-Valued Lukasiewicz Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:54-59 [Conf]
  10. Helmut Thiele
    On the Definition of Modal Operators in Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:62-67 [Conf]
  11. Zhenfeng Wang, Dongming Jin, Zhijian Li
    Single-Chip Realization of a Fuzzy Logic Controller with Neural Network Structure (NNFLC). [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:68-73 [Conf]
  12. Laurent Lemaitre, Marek J. Patyra, Daniel Mlynek
    Synthesis and Design Automation of Analog Fuzzy Logic VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:74-79 [Conf]
  13. Haomin Wu, Nan Zhuang, Marek A. Perkowski
    Novel CMOS Scan Design for VLSI Testability. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:82-86 [Conf]
  14. Yasunori Nagata, Chushin Afuso
    A Method of Test Pattern Generation for Multiple-Valued PLA's. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:87-91 [Conf]
  15. Naotake Kamiura, Yutaka Hata, Kazuharu Yamato
    A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:92-97 [Conf]
  16. Dan A. Simovici, Corina Reischer
    On Functional Entropy. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:100-104 [Conf]
  17. Akihiro Nozaki, Grant Pogosyan, Masahiro Miyakawa, Ivo G. Rosenberg
    Semirigid Sets of Quasilinear Clones. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:105-110 [Conf]
  18. Renren Liu
    Some Results on the Decision and Construction for Sheffer Functions in Partial K-Valued Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:111-116 [Conf]
  19. Sami B. Abugharbieh, Samuel C. Lee
    A Fast Algorithm for the Disjunctive Decomposition of m-Valued Functions Part I: The Decomposition Algorithm. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:118-125 [Conf]
  20. Sami B. Abugharbieh, Samuel C. Lee
    A Fast Algorithm for the Disjunctive Decomposition of m-Valued Functions Part II: Time Complexity Analysis. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:126-131 [Conf]
  21. Ning Song, Marek A. Perkowski
    EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:132-137 [Conf]
  22. Takafumi Aoki
    Dreams for New-Device-Based Superchips: From Transistors to Enzymes. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:140-149 [Conf]
  23. Shinji Karasawa, Kazuhiko Yamanouchi
    Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair Shaped I-V Curved Device as a Coupling Element. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:152-157 [Conf]
  24. Ming-Huei Shieh, Hung Chang Lin
    Series Resonant Tunneling Diodes as a Two-Dimensional Memory Cell. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:158-163 [Conf]
  25. Lutz J. Micheel, Albert H. Taddiken, Alan C. Seabaugh
    Multiple-Valued Logic Computation Circuits Using Micro- and Nanoelectronic Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:164-169 [Conf]
  26. Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi
    A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:170-175 [Conf]
  27. K. Wayne Current
    Multiple Valued Logic: Current-Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:176-181 [Conf]
  28. Kiyotaka Miyai, Yutaka Hata, Kazuharu Yamato
    A Representation of Approximate Reasoning with Analogy. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:184-189 [Conf]
  29. Shyi-Ming Chen
    An Inexact Reasoning Technique Using Linguistic Rule Matrix Transformations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:190-195 [Conf]
  30. Zheng Tang, Okihiko Ishizuka, Qi-xin Cao, Hiroki Matsumoto
    Algebraic Properties of a Learning Multiple-Valued Logic Network. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:196-201 [Conf]
  31. Qi-xin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
    Algorithm and Implementation of a Learning Multiple-Valued Logic Network. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:202-207 [Conf]
  32. Matthias Baaz, Christian G. Fermüller, Richard Zach
    Systematic Construction of Natural Deduction Systems for Many-Valued Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:208-213 [Conf]
  33. Daniel Etiemble, K. Navi
    A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:216-221 [Conf]
  34. Yutaka Hata, Kazuharu Yamato
    Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:222-227 [Conf]
  35. Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller
    Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:228-233 [Conf]
  36. Benchu Fei, Qinhua Hong, Nan Zhuang
    Calculation of Ternary Mixed Polarity Function Vector. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:236-238 [Conf]
  37. Xiexiong Chen, Claudio Moraga
    An Algebra for Current-Mode CMOS Multivalued Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:239-244 [Conf]
  38. Zeljko Zilic, Zvonko G. Vranesic
    Current-Mode CMOS Galois Field Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:245-250 [Conf]
  39. Dan A. Simovici, Ivan Stojmenovic, Ratko Tosic
    Functional Completeness and Weak Completeness in Set Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:251-256 [Conf]
  40. Jonathan Wayne Mills
    Lukasiewicz' Insect: The Role of Continuous-Valued Logic in a Mobile Robot's Sensors, Control, and Locomotion. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:258-263 [Conf]
  41. Babak A. Taheri
    CMOS Implementation and Fabrication of the Pseudo Analog Neuron. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:266-270 [Conf]
  42. Takafumi Aoki, Tatsuo Higuchi
    Impact of Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:271-276 [Conf]
  43. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Set-Valued Logic Networks for Wave-Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:277-282 [Conf]
  44. Masami Nakajima, Michitaka Kameyama
    Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:283-288 [Conf]
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