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Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
2006 (conf/ismvl/2006)


  1. Message from the Program Chair. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:- [Conf]

  2. List of Reviewers. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:- [Conf]

  3. Message from the Symposium Chairs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:- [Conf]

  4. Organizing Committee. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:- [Conf]
  5. Tsutomu Sasao
    Design Methods for Multiple-Valued Input Address Generators. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:1- [Conf]
  6. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:2- [Conf]
  7. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    On Designs of Radix Converters Using Arithmetic Decompositions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:3- [Conf]
  8. Eun-Ju Choi, Kyoung-Rok Cho, Je-Hoon Lee
    New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:4- [Conf]
  9. Akira Mochizuki, Takahiro Hanyu
    Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:5- [Conf]
  10. Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
    Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:6- [Conf]
  11. Sergiu Rudeanu, Dan A. Simovici
    On the Ranges of Algebraic Functions in Lattices - A Preliminary Report. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:7- [Conf]
  12. Hisayuki Tatsumi, Masahiro Miyakawa, Masao Mukaidono
    Upper and Lower Bounds on the Number of Disjunctive Forms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:8- [Conf]
  13. Matthias Baaz, Norbert Preining, Richard Zach
    Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:9- [Conf]
  14. Daniel Stamate
    Assumption based multi-valued semantics for extended logic programs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:10- [Conf]
  15. Tsutomu Sasao, Jon T. Butler
    Implementation of Multiple-Valued CAM Functions by LUT Cascades. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:11- [Conf]
  16. Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu
    The new architecture of radix-4 Chinese abacus adder. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:12- [Conf]
  17. Haque Mohammad Munirul, Michitaka Kameyama
    Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:13- [Conf]
  18. Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu
    Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:14- [Conf]
  19. los Roberto Mingoto Jr.
    A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:15- [Conf]
  20. Jaakko Astola, Radomir S. Stankovic
    Signal Processing Algorithms and Multiple-Valued Logic Design Methods. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:16- [Conf]
  21. Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
    Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:17- [Conf]
  22. Henning Gundersen, Yngvar Berg
    A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:18- [Conf]
  23. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
    A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:19- [Conf]
  24. Mitsuhiro Tanihata, Takao Waho
    A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:20- [Conf]
  25. Jovanka Pantovic, Gradimir Vojvodic
    Commuting Hyperoperations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:21- [Conf]
  26. Lucien Haddad, Hajime Machida, Ivo G. Rosenberg
    Theoretical Basis of Commutation Theory for Partial Clones. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:22- [Conf]
  27. Masahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi
    Associativity Test in Hypergroupoids. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:23- [Conf]
  28. Hajime Machida, Michael Pinsker
    Some Observations on Minimal Clones. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:24- [Conf]
  29. Görschwin Fey, Junhao Shi, Rolf Drechsler
    Efficiency of Multi-Valued Encoding in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:25- [Conf]
  30. Josep Argelich, Xavier Domingo, Chu-Min Li, Felip Manyà, Jordi Planes
    Towards Solving Many-Valued MaxSAT. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:26- [Conf]
  31. Elena Dubrova
    Random Multiple-Valued Networks: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:27- [Conf]
  32. Tsutomu Sasao, Shinobu Nagayama
    Representations of Elementary Functions Using Binary Moment Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:28- [Conf]
  33. Svetlana N. Yanushkevich, Vlad P. Shmerko, O. R. Boulanov
    Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:29- [Conf]
  34. D. Michael Miller, Mitchell A. Thornton
    QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:30- [Conf]
  35. Bogdan J. Falkowski, Shixing Yan
    Arithmetic-Haar Spectral Transform Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:31- [Conf]
  36. Michael Katz
    Multi-Valued Quantum Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:32- [Conf]
  37. Lun Li, Mitchell A. Thornton, Marek A. Perkowski
    A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:33- [Conf]
  38. Bogdan J. Falkowski, Cheng Fu
    Generation and Relation of Quaternary and Binary Linearly Independent Transforms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:34- [Conf]
  39. Claudio Moraga, Radomir S. Stankovic, Jaakko Astola
    Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:35- [Conf]
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