Conferences in DBLP
Claudi Alsina As You Like Them: Connectives in Fuzzy Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:2-0 [Conf ] Rolf Drechsler Verification of Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:10-15 [Conf ] Zeljko Zilic , Zvonko G. Vranesic New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:16-23 [Conf ] Susanto Rahardja , Bogdan J. Falkowski Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:24-0 [Conf ] Antonio di Nola Non-Archimedean Models of Lukasiewicz Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:32-36 [Conf ] Noboru Takagi , Kyoichi Nakashima , Masao Mukaidono A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:37-42 [Conf ] Robert J. Bignall , M. Spinks Propositional Skew Boolean Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:43-0 [Conf ] L. J. de Miguel , Margarita Mediavilla , Jose Ramón Perán González Fault Diagnosis System Based on Sensitivity Analysis and Fuzzy Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:50-55 [Conf ] Elena Dubrova , Jon C. Muzio Testability of Generalized Multiple-Valued Reed-Muller Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:56-61 [Conf ] Mou Hu Design of One-Vector Testable Binary Systems Based on Ternary Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:62-0 [Conf ] Takao Waho , Kevin J. Chen , Masafumi Yamamoto A Literal Gate Using Resonant-Tunneling Devices. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:68-73 [Conf ] Ali Sheikholeslami , P. Glenn Gulak , Takahiro Hanyu A Multiple-Valued Ferroelectric Content-Addressable Memory. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:74-79 [Conf ] Lutz J. Micheel , Hans L. Hartnagel Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:80-85 [Conf ] K. Wayne Current , Vojin G. Oklobdzija , Dragan Maksimovic Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:86-0 [Conf ] Noriaki Muranaka , Shigenobu Arai , Shigeru Imanishi , D. Michael Miller A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:92-97 [Conf ] Mostafa H. Abd-El-Barr , M. N. Hasan New MVL-PLA Structures Based on Current-Mode CMOS Technology. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:98-103 [Conf ] Masami Nakajima , Michitaka Kameyama Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:104-109 [Conf ] Come Rozon On the Use of VHDL as a Multi-Valued Logic Simulator. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:110-0 [Conf ] Reiner Hähnle Commodious Axiomatization of Quantifiers in Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:118-123 [Conf ] Weiru Liu The Incidence Propagation Method. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:124-129 [Conf ] Herman Akdag , Myriam Mokhtari Approximative Conjunctions Processing by Multi-Valued Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:130-135 [Conf ] Matthias Baaz , Christian G. Fermüller Intuitionistic Counterparts of Finitely-Valued Logics. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:136-0 [Conf ] G. Malinowski Helena Rasiowa - A View of the Academic Trajectory and the Influence upon Polish and the International Scientific Community. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:144-146 [Conf ] Josep Maria Font On the Contributions of Helena Rasiowa to Mathematical Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:147- [Conf ] Ton Sales From Pure to Approximate Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:148-0 [Conf ] V. Cutello , E. Molina , J. Montero Associativeness versus Recursiveness. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:154-159 [Conf ] Hassan Bezzazi , Ramón Pino Pérez Rational Transitivity and its Models. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:160-165 [Conf ] Dan A. Simovici , Corina Reischer Several Remarks on the Complexity of Set-Valued Switching Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:166-0 [Conf ] Alberto Bugarín , Purificación Cariñena , Manuel Fernández Delgado , Senén Barro Petri Net Representation of Fuzzy Reasoning under Incomplete Information. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:172-177 [Conf ] S. Lehmke Weight Structures for Approximate Reasoning with Weighted Expressions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:178-183 [Conf ] Salem Benferhat , Didier Dubois , Henri Prade Reasoning in Inconsistent Stratified Knowledge Bases. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:184-0 [Conf ] Lotfi A. Zadeh Inference in Fuzzy Logic via Generalized Constraint Propagation. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:192-0 [Conf ] Helmut Thiele On Isomorphisms between the Lattice of Tolerance Relations and Lattices of Clusterings. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:198-202 [Conf ] Ivo G. Rosenberg An Algebraic Approach to Hyperalgebras. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:203-0 [Conf ] Yasushi Yuminaka , Yoshisato Sasaki , Takafumi Aoki , Tatsuo Higuchi Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:210-215 [Conf ] Wenjun Wang , Claudio Moraga Design of Multivalued Circuits using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:216-0 [Conf ] Takahiro Hanyu , Manabu Arakaki , Michitaka Kameyama Quaternary Universal-Literal CAM for Cellular Logic Image Processing. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:224-229 [Conf ] Hao Tang , Hung Chang Lin Multi-Valued Decoder Based on Resonant Tunneling Diodes in Current Tapping Mode. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:230-0 [Conf ] Jon T. Butler , J. L. Nowlin , Tsutomu Sasao Planarity in ROMDD's of Multiple-Valued Symmetric Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:236-241 [Conf ] D. Michael Miller , Noriaki Muranaka Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:242-247 [Conf ] Tsutomu Sasao , Jon T. Butler A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:248-254 [Conf ] Bogdan J. Falkowski , Susanto Rahardja Complex Spectral Decision Diagrams. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:255-0 [Conf ] B. A. Romov Polynomial Completeness Criteria in Finite Boolean Algebras. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:262-266 [Conf ] Vlad P. Shmerko , Svetlana N. Yanushkevich , Vitaly G. Levashenko , I. Bondar Technique of Computing Logic Derivatives for MVL-Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:267-272 [Conf ] Lucien Haddad , Jean Fugère On the Lattice of Partial Clones on a Finite Set. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:273-278 [Conf ] F. Sokhatsky The Deepest Repetition-Free Decompositions of Non-Singular Functions of Finite-Valued Logics. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:279-0 [Conf ] Stefan Gerberding DT - An Automated Theorem Prover for Multiple-Valued First-Order Predicate Logics. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:284-289 [Conf ] Kyoichi Nakashima , Y. Nakamura , Noboru Takagi Logic Expressions of Monotonic Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:290-295 [Conf ] Grant Pogosyan Efficiently Irreducible Bases in Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:296-301 [Conf ] Elena N. Zaitseva , Tatiana Kalganova , Evgeny G. Kochergov Logical Not Polynomial Forms to Represent Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:302-307 [Conf ]