Conferences in DBLP
Anthony S. Wojcik Reasoning About Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Yuminaka , Takafumi Aoki , Tatsuo Higuchi Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Yasushi Kojima , Tatsuo Higuchi A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Tatsuo Higuchi A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Lun J. Hu Application of Multi-Zero Artificial Neural Network to the Design of an M-Valued Digital Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Ingo Schäfer , Marek A. Perkowski Multiple-Valued Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Bignall A Non-Commutative Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Masaharu Yuhara , Fujio Miyawaki , Kazuharu Yamato On the Complexity of Enumerations for Multiple-Valued Kleenean Functions and Unate Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Masao Mukaidono Fundamental Properties of Kleene-Stone Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Lluis Godo , Francesc Esteva , Pere Garcia , Jaume Agustí-Cullell A Formal Semantical Approach to Fuzzy Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Nakamura Topological Soft Algebra for the S5-Modal Fuzzy Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Tatsuki Watanabe , Masayuki Matsumoto Recognition of Circle Form Using Fuzzy Sequential System. [Citation Graph (0, 0)][DBLP ] Conf ] Jon T. Butler , Kriss A. Schueller Worst Case Number of Terms in Symmetric Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiteru Okura , Ryosaku Shimada , Toshiharu Hasegawa Quaternary Cyclic AN Codes for Burst Error Correction. [Citation Graph (0, 0)][DBLP ] Conf ] Ratko Tosic , Ivan Stojmenovic , Masahiro Miyakawa On the Maximum Size of the Terms in the Realization of Symmetric Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Watanabe , James R. Symon , Wayne D. Dettloff , Kathy E. Yount VLSI Fuzzy Chip and Inference Accelerator Board Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Young-hoon Chang , Jon T. Butler The Design of Current Mode CMOS Multiple-Valued Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Okihiko Ishizuka , Hiroshi Takarabe , Zheng Tang , Hiroki Matsumoto Synthesis of Current-Mode Pass Transistor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad Lei , Zvonko G. Vranesic On the Synthesis of 4-Valued Current Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Come Rozon , H. T. Mouftah Testability Analysis of CMOS Temary Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Corina Reischer , Dan A. Simovici On the Implementation of Set-Valued Non-Boolean Switching Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Takafumi Aoki , Michitaka Kameyama , Tatsuo Higuchi Design of Interconnection-Free Biomolecular Computing System. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Moraga A Decade of Spectral Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sen Jung Wei , Hung Chang Lin Multiple Peak Resonant Tunneling Diode for Multi-Valued Memory. [Citation Graph (0, 0)][DBLP ] Conf ] K. Wayne Current , M. E. Hurlston A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Babak A. Taheri Proposed CMOS VLSI Implementation of an Electronic Neuron Using Multivalued Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Xunwei Wu , Xiaowei Deng Theory of Grounded Current Switches and Quatemary IIL Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Neufeld The Abnormality Predicate. [Citation Graph (0, 0)][DBLP ] Conf ] Frank J. Wroblewski Undecidability in the Completion of Truth-Function Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Neil V. Murray , Erik Rosenthal Improving Tableau Deductions in Multiple-Valued Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner Hähnle Uniform Notation of Tableau Rules for Multiple-Valued Logics. [Citation Graph (0, 0)][DBLP ] Conf ] George Epstein , Helena Rasiowa Theory and Uses of Post Algebras of Order \omega+\omega\ast. Part II. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ran Zhang NPN Calculi: A Family of Three Strict Q-Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinand Börner , Lucien Haddad , Reinhard Pöschel A Note on Minimal Partial Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard W. Dueck , G. H. John van Rees On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathy P. Tirumalai , Varadarajan G. Vadakkencherry Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ewa Orlowska Post Relation Algebras and Their Proof System. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Rine An Equational Logic Approach for Mapping Multiple-Valued Rule-Based Expert Systems into Hardware Specification Rules. [Citation Graph (0, 0)][DBLP ] Conf ] C. Lucas , I. Burhan Türksen , Kenneth C. Smith A General-Purpose Inference Processor for Real-Time Intelligent Controllers Using Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshifumi Tsuchiya An Algorithm for the Solution of Multi-Valued Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Kawahito , K. Mizuno , Tasuro Nakamura Multiple-Valued Current-Mode Arithmetic Circuits Based on Redundant Positive-Digit Number Representations. [Citation Graph (0, 0)][DBLP ] Conf ] T. Raju Damarla , Fiaz Hossain Spectral Techniques for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh Optimization of Fuzzy Logic Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Sasaki , Fumio Ueno A Fuzzy Logic Function Generator (FLUG) Implemented with Current Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chyan Yang , Han-Chung Lu , David E. Gilbert An Investigation into the Implementation Costs of Residue and High Radix Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa H. Abd-El-Barr , H. Choy , A. K. Jain , R. J. Bolton A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions. [Citation Graph (0, 0)][DBLP ] Conf ] 