Conferences in DBLP
Takashi Okuda Advanced Circuit Technology to Realize Post Giga-bit DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Toshio Baba , Tetsuya Uemura Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiro Itoh , Takao Waho , K. Maezawa , Masafumi Yamamoto Ultrafast Ternary Quantizer using Resonant Tunneling Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Mititada Morisue , Jun Endo , Toshimitu Morooka , Nobuhiro Shimizu , Masahiro Sakamoto A Josephson Ternary Memory Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] I. Takanami A Note on Realizing Multiple-Valued Logic Functions using Akers' Cells - Cell Sizes and Path Lengths. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Song , Marek A. Perkowski Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Nagata , D. Michael Miller , Masao Mukaidono Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Tsutomu Sasao Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] D. Miller , Rolf Drechsler Implementing a Multiple-Valued Decision Diagram Package. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Macchiarulo , Pierluigi Civera Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] H. Chung , S. Pi , S. Rey The MacLaurin's and Taylor's Series Expansions of the Symbolic Multiple Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Takagi , Akimitsu Hon-nami , Kyoichi Nakashima A Characterization of r-Valued Functions Monotonic in an Order Based on Regularity. [Citation Graph (0, 0)][DBLP ] Conf ] Renren Liu Some Results on the Decision for Sheffer Functions in Partial K-Valued Logic(II). [Citation Graph (0, 0)][DBLP ] Conf ] Jon T. Butler , Tsutomu Sasao On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Moraga , Wenjun Wang Evolutionary Methods in the Design of Quaternery Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Per Lindgren , Rolf Drechsler , Bernd Becker Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Bignall , M. Spinks Multiple-Valued Logics for Theorem-Proving in First Order Logic with Equality. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Baaz , Richard Zach Compact Propositional Gödel Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Seiki Akama , Jair Minoro Abe Many-Valued and Annotated Modal Logics. [Citation Graph (0, 0)][DBLP ] Conf ] Zvonko G. Vranesic The FPGA Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Shen , Koichi Tanno , Okihiko Ishizuka , Zheng Tang Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Takahiro Saito , Michitaka Kameyama Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Takafumi Aoki , Tatsuo Higuchi Set-Valued Logic Circuits for Next Generation VLSI Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Yuminaka , Yoshisat Sasaki , Takafumi Aoki , Tatsuo Higuchi Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Hata , Makoto Ishikawa , Naotake Kamiura Image Segmentation Based on Kleene Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Alioune Ngom , Corina Reischer , Dan A. Simovici , Ivan Stojmenovic Learning with Permutably Homogenous Multiple-Valued Multiple-Threshold Perceptrons. [Citation Graph (0, 0)][DBLP ] Conf ] Craig M. Files , Marek A. Perkowski An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Craig M. Files , Marek A. Perkowski Multi-Valued Functional Decomposition as a Machine Learning Method. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski Fast Multi-Polarity Complex Hadamard Transform for Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic , Dragan Jankovic , Claudio Moraga Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence J. Thaden Constructing an MVL Patterned after Boolean Logic using a Practical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Yamamoto A Synthesis Method of the Approximate Reasoning Engine by means of Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Alioune Ngom , Ivan Stojmenovic , Zoran Obradovic Minimization of Multivalued Multithreshold Perceptrons using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Keim , Nicole Drechsler , Rolf Drechsler , Bernd Becker Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] P. Glenn Gulak A Review of Multiple-Valued Memory Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hozumi , Osamu Kakusho , Yutaka Hata On Low Cost Realization of Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Blair Fraser , Gerhard W. Dueck Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa I. Abd-El-Barr , Muhammad M. Abd-El-Barr A Frontier Algorithm for Optimization of Multiple-Valued Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Pogosyan , T. Nakamura e-Bases of Triadic Logic Operations. [Citation Graph (0, 0)][DBLP ] Conf ] V. Cheushev , Vlad P. Shmerko , Dan A. Simovici , Svetlana N. Yanushkevich Functional Entropy and Decision Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Sheikholeslami , R. Yoshimura , P. Glenn Gulak Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Hanyu , Kaname Teranishi , Michitaka Kameyama Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Shugang Wei , Kensuke Shimizu Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuhiko Shimabukuro , C. Zukeran Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyuki Araki , Hisayuki Tatsumi , Masao Mukaidono , F. Yamamoto Minimization of Incompletely Specified Regular Ternary Logic Functions and its Application to Fuzzy Switching Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hisayuki Tatsumi , Tomoyuki Araki , Masao Mukaidono , Shinji Tokumasu Upper and Lower Bounds on the Number of Fuzzy/c Switching Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Thiele On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Yukari Yamauchi , Masao Mukaidono A Study on Operations in Interval and Paired Probabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Tadashi Shibata Functional-Device-Based VLSI for Intelligent Electronic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo G. Rosenberg Multiple-Valued Hyperstructures. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Yamakawa A Novel Nonlinear Synapse Neuron Model Guaranteeing a Global Minimum - Wavelet Neuron. [Citation Graph (0, 0)][DBLP ] Conf ] Cengiz Kahraman , Ethem Tolga Data Envelopment Analysis using Fuzzy Concept. [Citation Graph (0, 0)][DBLP ] Conf ] F. Wakui , M. Hirano A Proposal and an Application of a Career-Mode Membership Function. [Citation Graph (0, 0)][DBLP ] Conf ] Masataka Tokumaru , K. Yamashita , Noriaki Muranaka , Shigeru Imanishi Membership Functions in Automatic Harmonization System. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Yutaka Hata , Kazuharu Yamato On Concurrent Tests of Fuzzy Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinand Börner , Lucien Haddad Generating Sets for Clones and Partial Clones. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Fugère , Lucien Haddad On Partial Clones Containing All Idempotent Partial Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Hajime Machida Some Continuous Maps on the Space of Clones in Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Akihiro Nozaki , Vaktang Lashkia A Finite Basis of the Set of All Monotone Partial Functions Defined over a Finite Poset. [Citation Graph (0, 0)][DBLP ] Conf ] 