|
|
Conferences in DBLP
(ispass)
2004 (conf/ispass/2004)
- Yale N. Patt
Opening and keynote 1. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:1- [Conf]
- Hans Vandierendonck, Koen De Bosschere
Eccentric and fragile benchmarks. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:2-11 [Conf]
- Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin
Communication breakdown: analyzing CPU usage in commercial Web workloads. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:12-19 [Conf]
- Erik Berg, Erik Hagersten
StatCache: a probabilistic approach to efficient and accurate data locality analysis. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:20-27 [Conf]
- Pavan Balaji, Sundeep Narravula, Karthikeyan Vaidyanathan, Savitha Krishnamoorthy, Jiesheng Wu, Dhabaleswar K. Panda
Sockets Direct Protocol over InfiniBand in clusters: is it beneficial? [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:28-35 [Conf]
- Leonardo R. Bachega, José R. Brunheroto, L. DeRose, Pedro Mindlin, José E. Moreira
The BlueGene/L pseudo cycle-accurate simulator. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:36-44 [Conf]
- Michael Van Biesbrouck, Timothy Sherwood, Brad Calder
A co-phase matrix to guide simultaneous multithreading simulation. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:45-56 [Conf]
- Jeremy Lau, Stefan Schoenmackers, Brad Calder
Structures for phase classification. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:57-67 [Conf]
- Gordon B. Bell, Mikko H. Lipasti
Deconstructing commit. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:68-77 [Conf]
- Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho, Michael C. Huang
Dynamically reducing pressure on the physical register file through simple register sharing. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:78-87 [Conf]
- Ying Zheng, Brian T. Davis, Matthew Jordan
Performance evaluation of exclusive cache hierarchies. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:89-96 [Conf]
- C. Anderson
Keynote II. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:97- [Conf]
- Irina Chihaia, Thomas R. Gross
Effectiveness of simple memory models for performance prediction. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:98-105 [Conf]
- Rong Xu, Zhiyuan Li
Using cache mapping to improve memory performance handheld devices. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:106-114 [Conf]
- R. Bonilla-Lucas, Peter Plachta, Aamer Sachedina, Daniel Jiménez-González, Calisto Zuzarte, Josep-Lluis Larriba-Pey
Characterization of the data access behavior for TPC-C traces. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:115-122 [Conf]
- Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge
Cache implications of aggressively pipelined high performance microprocessors. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:123-132 [Conf]
- Wei Huang, Witawas Srisa-an, J. Morris Chang
Dynamic pretenuring schemes for generational garbage collection. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:133-140 [Conf]
- Mikhail Dmitriev
Selective profiling of Java applications using dynamic bytecode instrumentation. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:141-150 [Conf]
- Russ Joseph, Margaret Martonosi, Zhigang Hu
Spectral analysis for characterizing program power and performance. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:151-160 [Conf]
- Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam
Compiler-directed physical address generation for reducing dTLB power. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:161-168 [Conf]
- Brad Calder, Daniel Citron, Yale N. Patt, J. Smith
The future of simulation: A field of dreams. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:169- [Conf]
- Lieven Eeckhout
Efficient architectural design of high performance microprocessors. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:170- [Conf]
- W. Wolf
Architectures and compilers for multimedia. [Citation Graph (0, 0)][DBLP]
ISPASS, 2004, pp:171- [Conf]
|
