Conferences in DBLP
Steven L. Teig Challenges and principles of physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Brenner , André Rohe An effective congestion driven placement framework. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh N. Adya , Igor L. Markov Consistent placement of macro-blocks using floorplanning and standard-cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffrey C.-F. Yeap Leakage current in low standby power and high performance devices: trends and challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek De Leakage-tolerant design techniques for high performance processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yongseok Cheon , D. F. Wong Design hierarchy guided multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Chih Chang , Jason Cong , David Zhigang Pan Physical hierarchy generation with routing congestion control. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh Routability driven white space allocation for fixed-die standard-cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Chiu-Wing Sham , Evangeline F. Y. Young Routability driven floorplanner with buffer block planning. [Citation Graph (0, 0)][DBLP ] Conf ] Faran Rafiq , Malgorzata Chrzanowska-Jeske , Hannah Honghua Yang , Naveed A. Sherwani Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. [Citation Graph (0, 0)][DBLP ] Conf ] Shuo Zhang , Wayne Wei-Ming Dai TEG: a new post-layout optimization method. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , Sachin S. Sapatnekar , Sani R. Nassif An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Mo Kang On-chip thermal engineering for peta-scale integration. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , Satyanarayan Gupta Shield count minimization in congested regions. [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Yuji Kukimoto , Chin-Chi Teng , Kurt Keutzer On convergence of switching windows computation in presence of crosstalk noise. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang Hu , Charles J. Alpert , Stephen T. Quay , Gopal Gandham Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Hrkic , John Lillis Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Chris C. N. Chu , Gopal Gandham , Milos Hrkic , Jiang Hu , Chandramouli V. Kashyap , Stephen T. Quay Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng A roadmap and vision for physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen Physical design with multiple on-chip voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Lauren Hui Chen , Malgorzata Marek-Sadowska Incremental delay change due to crosstalk noise. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Masao Takahashi , Hidetoshi Onodera Crosstalk noise optimization by post-layout transistor sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas Understanding and addressing the impact of wiring congestion during technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Chen , Andrew B. Kahng , Gabriel Robins , Alexander Zelikovsky Closing the smoothness and uniformity gap in area fill synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Stefanus Mantik , Igor L. Markov Min-max placement for large-scale timing optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Chang Wu Global clustering-based performance-driven circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] H. Chang , Eugene Shragowitz , Jian Liu , Habib Youssef , Bing Lu , Suphachai Sutanthavibul Net criticality revisited: an effective method to improve timing in physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Malgorzata Marek-Sadowska FAR: fixed-points addition & relaxation based placement. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong Timing closure based on physical hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Seokjin Lee , D. F. Wong Timing-driven routing for FPGAs based on Lagrangian relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Hui Xu , Rob A. Rutenbar , Karem A. Sakallah sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , Evangeline F. Y. Young Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Evangeline F. Y. Young , Chris C. N. Chu , Zion Cien Shen Twin binary sequences: a non-redundant representation for general non-slicing floorplan. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Daniel , Chin Siong Ong , Sok Chay Low , Kwok Hong Lee , Jacob White Geometrically parameterized interconnect performance models for interconnect synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] 