Conferences in DBLP
Raul Camposano Keynote Speaker. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Villarrubia Important placement considerations for modern VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Varadarajan Convergence of placement technology in physical synthesis: is placement really a point tool? [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Yuan Wang , Yu-Min Lee , Charlie Chung-Ping Chen 3D thermal-ADI: an efficient chip-level transient thermal simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Yuji Yamada , Hidetoshi Onodera Capturing crosstalk-induced waveform for accurate static timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli V. Kashyap , Charles J. Alpert , Frank Liu , Anirudh Devgan Closed form expressions for extending step delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Muzhou Shao , Martin D. F. Wong , Huijing Cao , Youxin Gao , Li-Pen Yuan , Li-Da Huang , Seokjin Lee Explicit gate delay model for timing evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , Ravi Vaidyanathan , Chanhee Oh , Rajendran Panda Signal integrity management in an SoC physical design flow. [Citation Graph (0, 0)][DBLP ] Conf ] Leon Stok , John Cohn There is life left in ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond Kirkpatrick The scaling challenge: can correct-by-construction design help? [Citation Graph (0, 0)][DBLP ] Conf ] Karthik Rajagopal , Tal Shaked , Yegna Parasuram , Tung Cao , Amit Chowdhary , Bill Halpin Timing driven force directed placement with physical net constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Malgorzata Marek-Sadowska Fine granularity clustering for large scale placement problems. [Citation Graph (0, 0)][DBLP ] Conf ] Guoqiang Chen , Sachin S. Sapatnekar Partition-driven standard cell thermal placement. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Xu Xu Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Michail Romesis , Min Xie Optimality, scalability and stability study of partitioning and placement algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh N. Adya , Mehmet Can Yildiz , Igor L. Markov , Paul Villarrubia , Phiroze N. Parakh , Patrick H. Madden Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond X. Nijssen , Ed P. Huijbregts A complete design for power methodology and flow for large ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Liebmann Layout impact of resolution enhancement techniques: impediment or opportunity? [Citation Graph (0, 0)][DBLP ] Conf ] Hardy Kwok-Shing Leung Advanced routing in changing technology landscape. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng Research directions for coevolution of rules and routers. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Feng , Dinesh P. Mehta , Hannah Honghua Yang Constrained "Modern" Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , Chung-Kuan Cheng , Jun Gu An integrated floorplanning with an efficient buffer planning algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Moe , Herman Schmit Floorplanning of pipelined array modules using sequence pairs. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou Efficient Steiner tree construction based on spanning graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Gopal Gandham , Milos Hrkic , Jiang Hu , Stephen T. Quay Porosity aware buffered steiner tree construction. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. [Citation Graph (0, 0)][DBLP ] Conf ] Bing Lu , Jiang Hu , Gary Ellis , Haihua Su Process variation aware clock tree routing. [Citation Graph (0, 0)][DBLP ] Conf ] Chetan Patel , Anthony Cozzie , Herman Schmit , Lawrence T. Pileggi An architectural exploration of via patterned gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Xun Yang , Zhiru Zhang Architecture and synthesis for multi-cycle communication. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Hailin Jiang , Qinghua Liu , Malgorzata Marek-Sadowska Synthesis and placement flow for gain-based programmable regular fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton Fishbone: a block-level placement and routing scheme. [Citation Graph (0, 0)][DBLP ] Conf ] 