Conferences in DBLP
Robert K. Montoye The four degrees of 3D. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:1- [Conf ] Ulrich Brenner , Anna Pauli , Jens Vygen Almost optimum placement legalization by minimum cost flow and dynamic programming. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:2-9 [Conf ] Haoxing Ren , David Zhigang Pan , David S. Kung Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:10-17 [Conf ] Andrew B. Kahng , Qinke Wang Implementation and extensibility of an analytic placer. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:18-25 [Conf ] Natarajan Viswanathan , Chris C. N. Chu FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:26-33 [Conf ] Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie Chen Multilevel routing with antenna avoidance. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:34-40 [Conf ] Hua Xiang , Kai-Yuan Chao , D. F. Wong An ECO algorithm for eliminating crosstalk violations. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:41-46 [Conf ] Charles J. Alpert , Milos Hrkic , Stephen T. Quay A fast algorithm for identifying good buffer insertion candidate locations. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:47-52 [Conf ] Dennis K. Y. Tong , Evangeline F. Y. Young Performance-driven register insertion in placement. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:53-60 [Conf ] Desmond Kirkpatrick , Pete Osler , Louis Scheffer , Prashant Saxena , Dennis Sylvester The great interconnect buffering debate: are you a chicken or an ostrich? [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:61- [Conf ] Mario R. Casu , Luca Macchiarulo Floorplanning for throughput. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:62-69 [Conf ] Andrew B. Kahng , Ion I. Mandoiu , Qinke Wang , Xu Xu , Alexander Zelikovsky Multi-project reticle floorplanning and wafer dicing. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:70-77 [Conf ] Jason Cong , Gabriele Nataneli , Michail Romesis , Joseph R. Shinnerl An area-optimality study of floorplanning. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:78-83 [Conf ] Ateen Khatkhate , Chen Li 0004 , Ameya R. Agnihotri , Mehmet Can Yildiz , Satoshi Ono , Cheng-Kok Koh , Patrick H. Madden Recursive bisection based mixed block placement. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:84-89 [Conf ] Takumi Okamoto , Tsutomu Kimoto , Naotaka Maeda Design methodology and tools for NEC electronics' structured ASIC ISSP. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:90-96 [Conf ] Deepak D. Sherlekar Design considerations for regular fabrics. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:97-102 [Conf ] Kun-Cheng Wu , Yu-Wen Tsai Structured ASIC, evolution or revolution? [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:103-106 [Conf ] Robert K. Montoye The four degrees of 3D. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:107- [Conf ] Shamik Das , Andy Fan , Kuan-Neng Chen , Chuan Seng Tan , Nisha Checka , Rafael Reif Technology, performance, and computer-aided design of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:108-115 [Conf ] Jaskirat Singh , Sachin S. Sapatnekar Topology optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:116-123 [Conf ] Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:124-131 [Conf ] Haifeng Qian , Sani R. Nassif , Sachin S. Sapatnekar Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:132-137 [Conf ] Monica Donno , Enrico Macii , Luca Mazzoni Power-aware clock tree planning. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:138-147 [Conf ] Taraneh Taghavi , Soheil Ghiasi , Abhishek Ranjan , Salil Raje , Majid Sarrafzadeh Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:148-155 [Conf ] Changbo Long , Jinjun Xiong , Lei He On optimal physical synthesis of sleep transistors. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:156-161 [Conf ] Rafael Escovar , Salvador Ortiz , Roberto Suaya Mutual inductance extraction and the dipole approximation. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:162-169 [Conf ] Lakshmi Kalpana Vakati , Janet Meiling Wang A new multi-ramp driver model with RLC interconnect load. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:170-175 [Conf ] Debjit Sinha , Hai Zhou , Chris C. N. Chu Optimal gate sizing for coupling-noise reduction. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:176-181 [Conf ] Kai Wang , Malgorzata Marek-Sadowska Clock network sizing via sequential linear programming with time-domain analysis. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:182-189 [Conf ] Peter J. Osler Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:190-197 [Conf ] Qinghua Liu , Malgorzata Marek-Sadowska A study of netlist structure and placement efficiency. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:198-203 [Conf ] Jurjen Westra , Chris Bartels , Patrick Groeneveld Probabilistic congestion prediction. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:204-209 [Conf ] Rupesh S. Shelar , Sachin S. Sapatnekar , Prashant Saxena , Xinning Wang A predictive distributed congestion metric and its application to technology mapping. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:210-217 [Conf ]