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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2004 (conf/ispd/2004)

  1. Robert K. Montoye
    The four degrees of 3D. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:1- [Conf]
  2. Ulrich Brenner, Anna Pauli, Jens Vygen
    Almost optimum placement legalization by minimum cost flow and dynamic programming. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:2-9 [Conf]
  3. Haoxing Ren, David Zhigang Pan, David S. Kung
    Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:10-17 [Conf]
  4. Andrew B. Kahng, Qinke Wang
    Implementation and extensibility of an analytic placer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:18-25 [Conf]
  5. Natarajan Viswanathan, Chris C. N. Chu
    FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:26-33 [Conf]
  6. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
    Multilevel routing with antenna avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:34-40 [Conf]
  7. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    An ECO algorithm for eliminating crosstalk violations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:41-46 [Conf]
  8. Charles J. Alpert, Milos Hrkic, Stephen T. Quay
    A fast algorithm for identifying good buffer insertion candidate locations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:47-52 [Conf]
  9. Dennis K. Y. Tong, Evangeline F. Y. Young
    Performance-driven register insertion in placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:53-60 [Conf]
  10. Desmond Kirkpatrick, Pete Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
    The great interconnect buffering debate: are you a chicken or an ostrich? [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:61- [Conf]
  11. Mario R. Casu, Luca Macchiarulo
    Floorplanning for throughput. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:62-69 [Conf]
  12. Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky
    Multi-project reticle floorplanning and wafer dicing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:70-77 [Conf]
  13. Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl
    An area-optimality study of floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:78-83 [Conf]
  14. Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden
    Recursive bisection based mixed block placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:84-89 [Conf]
  15. Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda
    Design methodology and tools for NEC electronics' structured ASIC ISSP. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:90-96 [Conf]
  16. Deepak D. Sherlekar
    Design considerations for regular fabrics. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:97-102 [Conf]
  17. Kun-Cheng Wu, Yu-Wen Tsai
    Structured ASIC, evolution or revolution? [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:103-106 [Conf]
  18. Robert K. Montoye
    The four degrees of 3D. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:107- [Conf]
  19. Shamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, Rafael Reif
    Technology, performance, and computer-aided design of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:108-115 [Conf]
  20. Jaskirat Singh, Sachin S. Sapatnekar
    Topology optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:116-123 [Conf]
  21. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:124-131 [Conf]
  22. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:132-137 [Conf]
  23. Monica Donno, Enrico Macii, Luca Mazzoni
    Power-aware clock tree planning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:138-147 [Conf]
  24. Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh
    Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:148-155 [Conf]
  25. Changbo Long, Jinjun Xiong, Lei He
    On optimal physical synthesis of sleep transistors. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:156-161 [Conf]
  26. Rafael Escovar, Salvador Ortiz, Roberto Suaya
    Mutual inductance extraction and the dipole approximation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:162-169 [Conf]
  27. Lakshmi Kalpana Vakati, Janet Meiling Wang
    A new multi-ramp driver model with RLC interconnect load. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:170-175 [Conf]
  28. Debjit Sinha, Hai Zhou, Chris C. N. Chu
    Optimal gate sizing for coupling-noise reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:176-181 [Conf]
  29. Kai Wang, Malgorzata Marek-Sadowska
    Clock network sizing via sequential linear programming with time-domain analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:182-189 [Conf]
  30. Peter J. Osler
    Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:190-197 [Conf]
  31. Qinghua Liu, Malgorzata Marek-Sadowska
    A study of netlist structure and placement efficiency. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:198-203 [Conf]
  32. Jurjen Westra, Chris Bartels, Patrick Groeneveld
    Probabilistic congestion prediction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:204-209 [Conf]
  33. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
    A predictive distributed congestion metric and its application to technology mapping. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:210-217 [Conf]
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