Conferences in DBLP
Andrew E. Caldwell , Andrew B. Kahng , Stefanus Mantik , Igor L. Markov , Alexander Zelikovsky On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Kia Bazargan , Samjung Kim , Majid Sarrafzadeh Nostradamus: a floorplanner of uncertain design. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Pileggi Timing metrics for physical design of deep submicron technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly Moore's law and physical design of ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Chris C. N. Chu , D. F. Wong Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Lei He An efficient technique for device and interconnect optimization in deep submicron designs. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet Aktuna , Rob A. Rutenbar , L. Richard Carley Device-level early floorplanning algorithms for RF circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Nagao , Takashi Kambe , Isao Shirakawa A layout approach to monolithic microwave IC. [Citation Graph (0, 0)][DBLP ] Conf ] S. Grout , G. Ledenbach , R. G. Bushroe , P. Fisher , D. Cottrell , D. Mallis , S. DasGupta , J. Morrell , Amrich Chokhavtia CHDStd - application support for reusable hierarchical interconnect timing views. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert The ISPD98 circuit benchmark suite. [Citation Graph (0, 0)][DBLP ] Conf ] S. DasGupta Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Evanthia Papadopoulou , D. T. Lee Critical area computation - a new approach. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Gabriel Robins , Anish Singh , Huijuan Wang , Alexander Zelikovsky Filling and slotting: analysis and algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph H. J. M. Otten Global wires: harmful?. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , Halim Theny Partitioning using second-order information and stochastic-gain functions. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaoyun Xing , Prithviraj Banerjee A parallel algorithm for zero skew clock tree routing. [Citation Graph (0, 0)][DBLP ] Conf ] Temo Chen , Michael K. H. Fan On convex formulation of the floorplan area minimization problem. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Niewczas , Wojciech Maly , Andrzej J. Strojwas A pattern matching algorithm for verification and analysis of very large IC layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Yang Huang , Yucheng Wang , Kwang-Ting Cheng LIBRA - a library-independent framework for post-layout performance optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar Bobba , Ibrahim N. Hajj Estimation of maximum current envelope for power bus analysis and design. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu New efficient algorithms for computing effective capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari , Massoud Pedram Calculation of ramp response of lossy transmission lines using two-port network functions. [Citation Graph (0, 0)][DBLP ] Conf ] Guang-Ming Wu , Yao-Wen Chang Switch-matrix architecture and routing for FPDs. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Murata , Ernest S. Kuh Sequence-pair based placement method for hard/soft/pre-placed modules. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Xu , Pei-Ning Guo , Chung-Kuan Cheng Rectilinear block placement using sequence-pair. [Citation Graph (0, 0)][DBLP ] Conf ] Maggie Zhiwei Kang , Wayne Wei-Ming Dai Topology constrained rectilinear block packing for layout reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng Futures for partitioning in physical design (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Le-Chin Eugene Liu , Hsiao-Ping Tseng , Carl Sechen Chip-level area routing. [Citation Graph (0, 0)][DBLP ] Conf ] Huibo Hou , Sachin S. Sapatnekar Routing tree topology construction to meet interconnect timing constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Tilmann Stöhr , Markus Alt , Asmus Hetzel , Jürgen Koehl Analysis, reduction and avoidance of crosstalk on VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] 