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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
1998 (conf/ispd/1998)

  1. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:4-11 [Conf]
  2. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:12-17 [Conf]
  3. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
    Nostradamus: a floorplanner of uncertain design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:18-23 [Conf]
  4. Lawrence T. Pileggi
    Timing metrics for physical design of deep submicron technologies. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:28-33 [Conf]
  5. Wojciech Maly
    Moore's law and physical design of ICs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:36- [Conf]
  6. Chris C. N. Chu, D. F. Wong
    Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:39-44 [Conf]
  7. Jason Cong, Lei He
    An efficient technique for device and interconnect optimization in deep submicron designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:45-51 [Conf]
  8. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
    Device-level early floorplanning algorithms for RF circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:57-64 [Conf]
  9. Akira Nagao, Takashi Kambe, Isao Shirakawa
    A layout approach to monolithic microwave IC. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:65-72 [Conf]
  10. S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, Amrich Chokhavtia
    CHDStd - application support for reusable hierarchical interconnect timing views. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:75-79 [Conf]
  11. Charles J. Alpert
    The ISPD98 circuit benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:80-85 [Conf]
  12. S. DasGupta
    Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel). [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:86- [Conf]
  13. Evanthia Papadopoulou, D. T. Lee
    Critical area computation - a new approach. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:89-94 [Conf]
  14. Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky
    Filling and slotting: analysis and algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:95-102 [Conf]
  15. Ralph H. J. M. Otten
    Global wires: harmful?. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:104-109 [Conf]
  16. Shantanu Dutt, Halim Theny
    Partitioning using second-order information and stochastic-gain functions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:112-117 [Conf]
  17. Zhaoyun Xing, Prithviraj Banerjee
    A parallel algorithm for zero skew clock tree routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:118-123 [Conf]
  18. Temo Chen, Michael K. H. Fan
    On convex formulation of the floorplan area minimization problem. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:124-128 [Conf]
  19. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    A pattern matching algorithm for verification and analysis of very large IC layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:129-134 [Conf]
  20. Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng
    LIBRA - a library-independent framework for post-layout performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:135-140 [Conf]
  21. Sudhakar Bobba, Ibrahim N. Hajj
    Estimation of maximum current envelope for power bus analysis and design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:141-146 [Conf]
  22. Andrew B. Kahng, Sudhakar Muddu
    New efficient algorithms for computing effective capacitance. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:147-151 [Conf]
  23. Payam Heydari, Massoud Pedram
    Calculation of ramp response of lossy transmission lines using two-port network functions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:152-157 [Conf]
  24. Guang-Ming Wu, Yao-Wen Chang
    Switch-matrix architecture and routing for FPDs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:158-163 [Conf]
  25. Hiroshi Murata, Ernest S. Kuh
    Sequence-pair based placement method for hard/soft/pre-placed modules. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:167-172 [Conf]
  26. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Rectilinear block placement using sequence-pair. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:173-178 [Conf]
  27. Maggie Zhiwei Kang, Wayne Wei-Ming Dai
    Topology constrained rectilinear block packing for layout reuse. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:179-186 [Conf]
  28. Andrew B. Kahng
    Futures for partitioning in physical design (tutorial). [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:190-193 [Conf]
  29. Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen
    Chip-level area routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:197-204 [Conf]
  30. Huibo Hou, Sachin S. Sapatnekar
    Routing tree topology construction to meet interconnect timing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:205-210 [Conf]
  31. Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl
    Analysis, reduction and avoidance of crosstalk on VLSI chips. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:211-218 [Conf]
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