
Conferences in DBLP
 Rajeev Madhavan
The death of logic synthesis. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:1 [Conf]
 Robert F. Lembach, Rafael A. ArceNazario, Donald Eisenmenger, Cory Wood
A diagnostic method for detecting and assessing the impact of physical design optimizations on routing. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:26 [Conf]
 JinYih Li, YihLang Li
An efficient tilebased ECO router with routing graph reduction and enhanced global routing flow. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:713 [Conf]
 Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
Routing of analog busses with parasitic symmetry. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:1419 [Conf]
 Di Wu, Jiang Hu, Rabi N. Mahapatra
Coupling aware timing optimization and antenna avoidance in layer assignment. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:2027 [Conf]
 Chris C. N. Chu, YiuChung Wong
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:2835 [Conf]
 Yukiko Kubo, Atsushi Takahashi
A global routing method for 2layer ball grid array packages. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:3643 [Conf]
 Stephen P. Boyd, SeungJean Kim
Geometric programming for circuit optimization. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:4446 [Conf]
 Baris Taskin, Ivan S. Kourtev
Delay insertion method in clock skew scheduling. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:4754 [Conf]
 Anand Rajaram, David Z. Pan, Jiang Hu
Improved algorithms for linkbased nontree clock networks for skew variability reduction. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:5562 [Conf]
 Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
Effects of onchip inductance on power distribution grid. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:6369 [Conf]
 Jaskirat Singh, Sachin S. Sapatnekar
A fast algorithm for power grid design. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:7077 [Conf]
 Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:7885 [Conf]
 Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
An efficient surfacebased lowpower buffer insertion algorithm. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:8693 [Conf]
 Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:94100 [Conf]
 Gary Smith
A new era for CAD. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:101 [Conf]
 JueHsien Chern
Challenges of analog/mixedsignal SoC design and verification. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:102 [Conf]
 Andrzej J. Strojwas
Tutorial on DFM for physical design. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:103 [Conf]
 TungChieh Chen, YaoWen Chang
Modern floorplanning based on fast simulated annealing. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:104112 [Conf]
 Jill H. Y. Law, Evangeline F. Y. Young
Multibend bus driven floorplanning. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:113120 [Conf]
 Mario R. Casu, Luca Macchiarulo
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:121128 [Conf]
 Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
Are floorplan representations important in digital design? [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:129136 [Conf]
 Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
An efficient technology mapping algorithm targeting routing congestion under delay constraints. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:137144 [Conf]
 Qinghua Liu, Malgorzata MarekSadowska
Wire length predictionbased technology mapping and fanout optimization. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:145151 [Conf]
 I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson
Mapping algorithm for largescale field programmable analog array. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:152158 [Conf]
 James D. Z. Ma, Rob A. Rutenbar
Fast intervalvalued statistical interconnect modeling and reduction. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:159166 [Conf]
 Brent Goplen, Sachin S. Sapatnekar
Thermal via placement in 3D ICs. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:167174 [Conf]
 Xin Yuan, Kevin W. McCullen, FookLuen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan
Technology migration technique for designs with strong RETdriven layout restrictions. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:175182 [Conf]
 Shankar Krishnamoorthy
Insights and perspectives on physical synthesis. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:183 [Conf]
 Paul Villarrubia
Physical design tools for hierarchy. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:184 [Conf]
 Tony Chan, Jason Cong, Kenton Sze
Multilevel generalized forcedirected method for circuit placement. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:185192 [Conf]
 Bo Yao, Hongyu Chen, ChungKuan Cheng, NanChi Chou, LungTien Liu, Peter Suaris
Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:193199 [Conf]
 Charles J. Alpert, Andrew B. Kahng, GiJoon Nam, Sherief Reda, Paul Villarrubia
A semipersistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:200207 [Conf]
 Andrew B. Kahng, Sherief Reda
Evaluation of placer suboptimality via zerochange netlist transformations. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:208215 [Conf]
 GiJoon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
The ISPD2005 placement contest and benchmark suite. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:216220 [Conf]
 Natarajan Viswanathan, Min Pan, Chris C. N. Chu
FastPlace: an analytical placer for mixedmode designs. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:221223 [Conf]
 Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov
Capo: robust and scalable opensource mincut floorplacer. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:224226 [Conf]
 Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
mPL6: a robust multilevel mixedsize placement engine. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:227229 [Conf]
 Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden
Recursive bisection placement: feng shui 5.0 implementation details. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:230232 [Conf]
 Andrew B. Kahng, Sherief Reda, Qinke Wang
APlace: a general analytic placement framework. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:233235 [Conf]
 TungChieh Chen, TienChang Hsu, ZheWei Jiang, YaoWen Chang
NTUplace: a ratio partitioning based placement algorithm for largescale mixedsize designs. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:236238 [Conf]
 Bo Hu, Yue Zeng, Malgorzata MarekSadowska
mFAR: fixedpointsadditionbased VLSI placement algorithm. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:239241 [Conf]
 Bernd Obermeier, Hans Ranke, Frank M. Johannes
Kraftwerk: a versatile placement approach. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:242244 [Conf]
 Taraneh Taghavi, Xiaojian Yang, BoKyung Choi
Dragon2005: largescale mixedsize placement tool. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:245247 [Conf]
