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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2005 (conf/ispd/2005)

  1. Rajeev Madhavan
    The death of logic synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:1- [Conf]
  2. Robert F. Lembach, Rafael A. Arce-Nazario, Donald Eisenmenger, Cory Wood
    A diagnostic method for detecting and assessing the impact of physical design optimizations on routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:2-6 [Conf]
  3. Jin-Yih Li, Yih-Lang Li
    An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:7-13 [Conf]
  4. Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
    Routing of analog busses with parasitic symmetry. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:14-19 [Conf]
  5. Di Wu, Jiang Hu, Rabi N. Mahapatra
    Coupling aware timing optimization and antenna avoidance in layer assignment. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:20-27 [Conf]
  6. Chris C. N. Chu, Yiu-Chung Wong
    Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:28-35 [Conf]
  7. Yukiko Kubo, Atsushi Takahashi
    A global routing method for 2-layer ball grid array packages. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:36-43 [Conf]
  8. Stephen P. Boyd, Seung-Jean Kim
    Geometric programming for circuit optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:44-46 [Conf]
  9. Baris Taskin, Ivan S. Kourtev
    Delay insertion method in clock skew scheduling. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:47-54 [Conf]
  10. Anand Rajaram, David Z. Pan, Jiang Hu
    Improved algorithms for link-based non-tree clock networks for skew variability reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:55-62 [Conf]
  11. Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
    Effects of on-chip inductance on power distribution grid. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:63-69 [Conf]
  12. Jaskirat Singh, Sachin S. Sapatnekar
    A fast algorithm for power grid design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:70-77 [Conf]
  13. Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
    Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:78-85 [Conf]
  14. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
    An efficient surface-based low-power buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:86-93 [Conf]
  15. Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
    Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:94-100 [Conf]
  16. Gary Smith
    A new era for CAD. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:101- [Conf]
  17. Jue-Hsien Chern
    Challenges of analog/mixed-signal SoC design and verification. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:102- [Conf]
  18. Andrzej J. Strojwas
    Tutorial on DFM for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:103- [Conf]
  19. Tung-Chieh Chen, Yao-Wen Chang
    Modern floorplanning based on fast simulated annealing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:104-112 [Conf]
  20. Jill H. Y. Law, Evangeline F. Y. Young
    Multi-bend bus driven floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:113-120 [Conf]
  21. Mario R. Casu, Luca Macchiarulo
    Floorplan assisted data rate enhancement through wire pipelining: a real assessment. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:121-128 [Conf]
  22. Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
    Are floorplan representations important in digital design? [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:129-136 [Conf]
  23. Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
    An efficient technology mapping algorithm targeting routing congestion under delay constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:137-144 [Conf]
  24. Qinghua Liu, Malgorzata Marek-Sadowska
    Wire length prediction-based technology mapping and fanout optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:145-151 [Conf]
  25. I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson
    Mapping algorithm for large-scale field programmable analog array. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:152-158 [Conf]
  26. James D. Z. Ma, Rob A. Rutenbar
    Fast interval-valued statistical interconnect modeling and reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:159-166 [Conf]
  27. Brent Goplen, Sachin S. Sapatnekar
    Thermal via placement in 3D ICs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:167-174 [Conf]
  28. Xin Yuan, Kevin W. McCullen, Fook-Luen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan
    Technology migration technique for designs with strong RET-driven layout restrictions. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:175-182 [Conf]
  29. Shankar Krishnamoorthy
    Insights and perspectives on physical synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:183- [Conf]
  30. Paul Villarrubia
    Physical design tools for hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:184- [Conf]
  31. Tony Chan, Jason Cong, Kenton Sze
    Multilevel generalized force-directed method for circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:185-192 [Conf]
  32. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
    Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:193-199 [Conf]
  33. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  34. Andrew B. Kahng, Sherief Reda
    Evaluation of placer suboptimality via zero-change netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:208-215 [Conf]
  35. Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
    The ISPD2005 placement contest and benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:216-220 [Conf]
  36. Natarajan Viswanathan, Min Pan, Chris C. N. Chu
    FastPlace: an analytical placer for mixed-mode designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:221-223 [Conf]
  37. Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov
    Capo: robust and scalable open-source min-cut floorplacer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:224-226 [Conf]
  38. Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: a robust multilevel mixed-size placement engine. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:227-229 [Conf]
  39. Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden
    Recursive bisection placement: feng shui 5.0 implementation details. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:230-232 [Conf]
  40. Andrew B. Kahng, Sherief Reda, Qinke Wang
    APlace: a general analytic placement framework. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:233-235 [Conf]
  41. Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
    NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:236-238 [Conf]
  42. Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska
    mFAR: fixed-points-addition-based VLSI placement algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:239-241 [Conf]
  43. Bernd Obermeier, Hans Ranke, Frank M. Johannes
    Kraftwerk: a versatile placement approach. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:242-244 [Conf]
  44. Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi
    Dragon2005: large-scale mixed-size placement tool. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:245-247 [Conf]
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