Conferences in DBLP
Ted Vucurevich Commercial CAD: challenges and opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Jinjun Xiong , Vladimir Zolotov , Lei He Robust extraction of spatial correlation. [Citation Graph (0, 0)][DBLP ] Conf ] B. Lasbouygues , Robin Wilson , Nadine Azémard , Philippe Maurine Timing analysis in presence of supply voltage and temperature variations. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Ankur Srivastava Probabilistic evaluation of solutions in variability-driven optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Shi , Hao Yu , Lei He SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. [Citation Graph (0, 0)][DBLP ] Conf ] Lizheng Zhang , Jun Shao , Charlie Chung-Ping Chen Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Lienig introduction to electromigration-aware physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM. [Citation Graph (0, 0)][DBLP ] Conf ] Zhe Feng 0002 , Yu Hu , Tong Jing , Xianlong Hong , Xiaodong Hu , Guiying Yan An O (n logn ) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. [Citation Graph (0, 0)][DBLP ] Conf ] Bor-Yiing Su , Yao-Wen Chang , Jiang Hu An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Yu Chen , Zhi-Da Lin NEMO: a new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Saeedi , Morteza Saheb Zamani , Ali Jahanian Prediction and reduction of routing congestion. [Citation Graph (0, 0)][DBLP ] Conf ] Jarrod A. Roy , James F. Lu , Igor L. Markov Seeing the forest and the trees: Steiner wirelength optimization in placemen. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Wei Liu , Yao-Wen Chang Floorplan and power/ground network co-synthesis for fast design convergence. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Chen , Lei He Noise driven in-package decoupling capacitor optimization for power integrity. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Bao Liu , Sheldon X.-D. Tan Efficient decoupling capacitor planning via convex programming methods. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Shi , Yici Cai , Sheldon X.-D. Tan , Xianlong Hong High accurate pattern based precondition method for extremely large power/ground grid analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Shanq-Jang Ruan , Edwin Naroska , Chun-Chih Chen Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen Efficient generation of short and fast repeater tree topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jinjun Xiong , Lei He Fast buffer insertion considering process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Beth L. Chen , Dmitri B. Chklovskii Placement and routing optimization in the brain. [Citation Graph (0, 0)][DBLP ] Conf ] Mongkol Ekpanyapong , Sung Kyu Lim Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Uday Padmanabhan , Janet Meiling Wang , Jiang Hu Statistical clock tree routing for robustness to process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Rajaram , David Z. Pan Variation tolerant buffered clock network synthesis with cross links. [Citation Graph (0, 0)][DBLP ] Conf ] P. V. Srinivas Chip assembly: a new paradigm in hierarchical physical design. [Citation Graph (0, 0)][DBLP ] Conf ] François Rémond Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Joon Nam ISPD 2006 Placement Contest: Benchmark Suite and Results. [Citation Graph (0, 0)][DBLP ] Conf ] Arjun Rajagopal Clock tree design challenges for robust and low power design. [Citation Graph (0, 0)][DBLP ] Conf ] Ad M. G. Peeters Clockless IC design using handshake technology. [Citation Graph (0, 0)][DBLP ] Conf ] Aaron N. Ng , Igor L. Markov , Rajat Aggarwal , Venky Ramachandran Solving hard instances of floorplacement. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuoyuan Li , Xianlong Hong , Qiang Zhou , Shan Zeng , Jinian Bian , Hannah Yang , Vijay Pitchumani , Chung-Kuan Cheng Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Sherief Reda , Amit Chowdhary Effective linear programming based placement methods. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichi Kouda , Chikaaki Kodama , Kunihiro Fujiyoshi Improved method of cell placement with symmetry constraints for analog IC layout design. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Li , Laleh Behjat Net cluster: a net-reduction based clustering preprocessing algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jarrod A. Roy , David A. Papa , Aaron N. Ng , Igor L. Markov Satisfying whitespace requirements in top-down placement. [Citation Graph (0, 0)][DBLP ] Conf ] Taraneh Taghavi , Xiaojian Yang , Bo-Kyung Choi , Maogang Wang , Majid Sarrafzadeh Dragon2006: blockage-aware congestion-controlling mixed-size placer. [Citation Graph (0, 0)][DBLP ] Conf ] Tony F. Chan , Jason Cong , Joseph R. Shinnerl , Kenton Sze , Min Xie mPL6: enhanced multilevel mixed-size placement. [Citation Graph (0, 0)][DBLP ] Conf ] Zhe-Wei Jiang , Tung-Chieh Chen , Tien-Chang Hsu , Hsin-Chen Chen , Yao-Wen Chang NTUplace2: a hybrid placer using partitioning and analytical techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Qinke Wang A faster implementation of APlace. [Citation Graph (0, 0)][DBLP ] Conf ] 