Conferences in DBLP
Charles J. Alpert , Tony F. Chan , Dennis J.-H. Huang , Andrew B. Kahng , Igor L. Markov , Pep Mulet , Kenneth Yan Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP ] Conf ] Huiqun Liu , D. F. Wong Network flow based multi-way partitioning with area and pin constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis J.-H. Huang , Andrew B. Kahng Partitioning-based standard-cell global placement with an exact objective. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Murata , Kunihiro Fujiyoshi , Mineo Kaneko VLSI/PCB placement with obstacles based on sequence-pair. [Citation Graph (0, 0)][DBLP ] Conf ] Guenter Stenz , Bernhard M. Riess , Bernhard Rohfleisch , Frank M. Johannes Timing driven placement in interaction with netlist transformations. [Citation Graph (0, 0)][DBLP ] Conf ] R. X. T. Nijssen , C. A. J. van Eijk Regular layout generation of logically optimized datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn Holt , Akhilesh Tyagi Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Guy G. Lemieux , Stephen Dean Brown , Daniel Vranesic On two-step routing for FPGAS. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Jun Cha , Chong S. Rim , Kazuo Nakajima A simple and effective greedy multilayer router for MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Patrick H. Madden Performance driven global routing for standard cell design. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Dong Cho A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Andrew B. Kahng , Kwok-Shing Leung Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP ] Conf ] C. Douglass Bateman , Christopher S. Helvig , Gabriel Robins , Alexander Zelikovsky Provably good routing tree construction with multi-port terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Scheffer A roadmap of CAD tool changes for sub-micron interconnect problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey L. Burns , Jack A. Feldman C5M - a control logic layout synthesis system for high-performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Fook-Luen Heng , Zhan Chen , Gustavo E. Téllez A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. [Citation Graph (0, 0)][DBLP ] Conf ] A. Bertolet , K. Carpenter , K. Carrig , A. Chu , A. Dean , F. Ferraiolo , S. Kenyon , D. Phan , J. Petrovick , G. Rodgers , D. Willmott , T. Bairley , T. Decker , V. Girardi , Y. Lapid , M. Murphy , P. A. Scott , R. Weiss A pseudo-hierarchical methodology for high performance microprocessor design. [Citation Graph (0, 0)][DBLP ] Conf ] Juho Kim , Cyrus Bamji , Yanbin Jiang , Sachin S. Sapatnekar Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Nevin Kapur , Debabrata Ghosh , Franc Brglez Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Fung Yu Young , D. F. Wong How good are slicing floorplans?. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathi Dasgupta , Susmita Sur-Kolay Slicibility of rectangular graphs and floorplan optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Alexander Power optimization for FPGA look-up tables. [Citation Graph (0, 0)][DBLP ] Conf ] Chris C. N. Chu , D. F. Wong A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Wen Tsay , Wen-Jong Fang , Allen C.-H. Wu , Youn-Long Lin Preserving HDL synthesis hierarchy for cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Rony Kay , Gennady Bucheuv , Lawrence T. Pileggi EWA: exact wiring-sizing algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] D. Zhou , X. Y. Liu Minimization of chip size and power consumption of high-speed VLSI buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Chris C. N. Chu , D. F. Wong Closed form solution to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Ernest S. Kuh Physical design: reminiscing and looking ahead. [Citation Graph (0, 0)][DBLP ] Conf ] T. C. Hu Physical design: mathematical models and methods. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano The quarter micron challenge: intergrating physical and logic design. [Citation Graph (0, 0)][DBLP ] Conf ] R. G. Bushroe , S. DasGupta , A. Dengi , P. Fisher , S. Grout , G. Ledenbach , N. S. Nagaraj , R. Steele Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , A. Richard Newton , Narendra V. Shenoy The future of logic synthesis and physical design in deep-submicron process geometries. [Citation Graph (0, 0)][DBLP ] Conf ] David P. LaPotin , Uttam Ghoshal , Eli Chiprout , Sani R. Nassif Physical design challenges for performance. [Citation Graph (0, 0)][DBLP ] Conf ] 